DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD98405
155M ATM INTEGRATED SAR CONTROLLER
DESCRIPTION
The
µ
PD98405 (NEASCOT-S20
TM
) is a high-performance SAR chip that performs segmentation and reassembly of
ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an
ABR function in hardware.
The
µ
PD98405 conforms to ATM Forum and has the functions of the AAL-5 SAR
sublayer, ATM layer, and TC sublayer.
FEATURES
• Conforms to ATM Forum.
• Host bus interface supporting PCI bus/generic bus.
-
-
PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1
Generic bus interface (5/3.3 V, 32 bits, 33 MHz)
• AAL-5 SAR sublayer, ATM layer, and TC sublayer functions
• Hardware support of AAL-5 processing
• Software support of non-AAL-5 traffic
• SONET STS-3c/SDH STM-1 155-Mbps framer function
• Clock recovery/clock synthesizer function
• Supports up to 32 K virtual channels (VCs)
• Sixteen traffic shapers for VBR for transmission scheduling
• Hardware support of CBR/VBR/ABR/UBR service
• Supports multi-cell burst transfer for transmission and reception
• MIB counter function
• Supports LAN emulation function
• Receive FIFO of 96 cells
• External PHY devices connectable: UTOPIA Level-1 interface
• 0.35-
µ
m CMOS process, +5-/3.3-V power supply
-
-
Bus interface +5 V: +5-/3.3-V power supply
Bus interface +3.3 V: +3.3-V power supply
• 304-pin plastic QFP
ORDERING INFORMATION
Part Number
Package
304-pin plastic QFP (0.5-mm fine pitch) (40
×
40 mm)
µ
PD98405GL-PMU
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S12689EJ2V0DS00 (2nd edition)
Date Published April 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997, 1999
µ
PD98405
PIN NAME
ABRT_B
ACK64_B
AD63-AD0
AGND
ASEL_B
ATTN_B
AV
DD3
BE3_B-BE0_B
CA18-CA0
CBE3_B-CBE0_B
CD31-CD0
CLK
COE_B
CPAR3-CPAR0
CWE_B
DEVSEL_B
DR/W_B
EMPTY_B/RCLAV
ERR_B
E2PCLK
E2PCS
E2PDI
E2PDO
FRAME_B
FULL_B/TCLAV
GND
GNT_B
HGND
HV
DD3
IDSEL
INITD
INTR_B
IRDY_B
JCK
JDI
JDO
JMS
JRST_B
OE_B
PAR
PAR3-PAR0
PAR64
PCI_MODE
: Abort
: Acknowledge 64-bit Transfer
: Address/Data
: Ground for Analog Part
: Slave Address Select
: Attention
: +3.3 V Power Supply for
Analog Part
: Byte Enable
: Control Memory Address
: Local Port Byte Enable
: Control Memory Data
: Clock
: Control Memory Output Enable
: Control Memory parity
: Control Memory Write Enable
: Device Select
: DMA Read/Write
: PHY Empty/Rx Cell Available
: Error
: Clock for EEPROM
: EEPROM Chip Select
: Serial Data Input from EEPROM
: Serial Data Output to EEPROM
: Cycle Frame
: PHY Buffer full/Tx Cell Available
: Ground for Digital Part
: Grant
: Ground for High-Speed Part
: +3.3 V Power Supply for
High-Speed Part
: ID Select
: Initialization Disable
: Interrupt
: Initiator Ready
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: JTAG Test Pin
: Output Enable
: Parity
: Bus Party
: Parity 64 bits
: PCI Mode
Rx7-Rx0
SCLK
SD
SEL_B
SERR_B
SIZE2-SIZE0
SR/W_B
STOP_B
TCLK
TDOC
TDOT
TENBL_B
TEST
TFKC
TFKT
TRDY_B
TSOC
Tx7-Tx0
V
DD3
V
DD5
PERR_B
PHCE_B
PHINT_B
PHOE_B
PHRST_B
PHR/W_B
PHYALM
RCLK
RCIC
RCIT
RDIC
RDIT
PDY_B
REFCLK
RENBL_B
REQ64_B
REQ_B
RGND
ROMCS_B
ROMOE_B
RSOC
RST_B
RV
DD3
: Parity Error
: PHY Chip Enable
: PHY Interrupt
: PHY Output Enable
: PHY Reset
: PHY Read/Write
: Physical Alarm
: Receive Clock
: Receive Clock Input Complement
: Receive Clock Input True
: Receive Data Input Complement
: Receive Data Input True
: Target Ready
: Reference Clock
: Receive Enable
: Request 64-bit Transfer
: Request
: Ground for Receive PLL Part
: Expansion ROM Chip Select
: Expansion ROM Output Enable
: Receive Start Cell
: Reset
: +3.3 V Power Supply for Receive
PLL Part
: Receive Data Bus
: SAR System Clock
: Signal Detect
: Slave Select
: System Error
: Burst Size
: Slave Read /Write
: Stop
: Transmit Clock
: Transmit Data Output Complement
: Transmit Data Output True
: Transmit Enable
: Test Mode Pin
: Transmit Reference Clock Complement
: Transmit Reference Clock True
: Target Ready
: Transmit Start of Cell
: Transmit Data Bus
: +3.3 V Power Supply for Digital Part
: +5 V Power Supply for Digital Part
ROMA15-ROMA0: Expansion ROM Address
ROMD7-ROMD0 : Expansion ROM Input Data
PCBE7_B-PCBE0_B: Bus Command and Byte Enables
Data Sheet S12689EJ2V0DS00
5
PCB设计
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