DATA SHEET
GaAs INTEGRATED CIRCUIT
µ
PG181GR
GaAs MMIC DBS Twin IF Switch
DESCRIPTION
The
µ
PG181GR is intended for use in Direct Broadcast Satellite (DBS) applications within the Low Noise Block
(LNB) down-converter for systems where at least two LNB outputs are required.
It offers two intermediate frequency amplifier channels that can independently select 1 of 2 IF inputs. It is loused
in a very small 16-pin plastic HTSSOP package available on tape-and-reel and easy to install and contributes to
miniaturizing the systems.
FEATURES
• Two Independent IF Channels
• Integral Switching to Channel Input to Either Channel Output
• Insertion Loss Per Channel
• Frequency Range
: 5.0 dB TYP. (Z
O
= 50
Ω)
: 950 MHz to 2 150 MHz
• Channel to Channel Isolation : 33 dB TYP.
• Small 16-pin HTSSOP Package
ORDERING INFORMATION (PLAN)
Part Number
Package
16-pin Plastic HTSSOP
Supplying Form
Carrier tape width 12 mm.
Qty 3 kp/reel.
µ
PG181GR-E1
Remark
To order evaluation samples, please contact your local NEC sales office. (Part number for sample
order:
µ
PG181GR)
Caution The IC must be handled with care to prevent static discharge because its circuit composed of
GaAs MES-FET.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. P14268EJ2V0DS00 (2nd edition)
Date Published November 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1999
µ
PG181GR
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
Parameter
Control Voltage 1, 2, 3, 4
Total Power Dissipation
Operating Ambient Temperature
Storage Temperature
Symbol
V
CONT1, 2, 3, 4
P
tot
T
A
T
stg
Ratings
−6
to +6
2
Note2
Note 1
Unit
V
W
°C
°C
−40
to +85
−65
to +150
Notes 1.
| V
CONT(H)
−
V
CONT(L)
|
≤
6.0 V
2.
Mounted on 50
×
50
×
1.6 mm double copper clad epoxy glass PWB, T
C
= +85
°C
PIN CONNECTION AND INTERNAL BLOCK DIAGRAM (TOP VIEW)
Pin No.
1
2
3
4
Connection
IN2
GND
GND
V
CONT3
Pin No.
5
6
7
8
Connection
V
CONT4
GND
GND
OUT2
Pin No.
9
10
11
12
Connection
OUT1
GND
GND
V
CONT2
Pin No.
13
14
15
16
Connection
V
CONT1
GND
GND
IN1
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
2
Data Sheet P14268EJ2V0DS00
µ
PG181GR
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
°
C)
Parameter
Control Voltage (High)
Control Voltage (Low)
Symbol
V
CONT(H)
V
CONT(L)
MIN.
+4.5
−0.5
TYP.
+5
0
MAX.
+5.5
+0.5
Unit
V
V
ELECTRICAL CHARACTERISTICS (T
A
= +25
°
C, unless otherwise specified: V
CONT1
to V
CONT4
=
0/ +5 V, Z
O
= 50
Ω
, LL, LR, RL, RR Each Port)
Parameter
Insertion Loss
Insertion Loss Flatness
Insertion Loss Flatness
Channel Isolation
Channel Isolation
Output Return Loss
Control Current
Symbol
L
INS
∆L
INS
∆L
INS
ISL
ISL
RL
out
I
CONT
Test Conditions
f = 0.95 GHz to 2.15 GHz
| L
INS
(0.95 GHz)
−
L
INS
(1.7 GHz) |
| L
INS
(0.95 GHz)
−
L
INS
(2.15 GHz) |
f = 0.95 GHz to 1.7 GHz
f = 1.7 GHz to 2.15 GHz
f = 0.95 GHz to 2.15 GHz
V
CONT
= +5 V/0 V, RF OFF
MIN.
−
−
−
30
25
13
−
TYP.
5.0
0.5
0.8
33
30
16
−
MAX.
7.0
1.2
1.5
−
−
−
200
Unit
dB
dB
dB
dB
dB
dB
µ
A
Data Sheet P14268EJ2V0DS00
3
µ
PG181GR
EVALUATION CIRCUIT
V
CONT1
to V
CONT4
= 0/ +5 V, Z
O
= 50
Ω
, DC Blocking Capacitor = 51 pF
V
CONT1
V
CONT2
C = 51 pF
IN1
(L)
Z
O
= 50
Ω
16
1 000 pF
1 000 pF
C = 51 pF
OUT1
Z
O
= 50
Ω
9
1
Z
O
= 50
Ω
IN2
(R)
C = 51 pF
V
CONT3
V
CONT4
1 000 pF
1 000 pF
8
Z
O
= 50
Ω
OUT2
C = 51 pF
CHANNEL SELECT TRUTH TABLE
Output
On Channel
OUT1
L
OUT2
L
IN1
−
OUT1
IN1
−
OUT2
IN1
−
OUT1
IN2
−
OUT2
IN2
−
OUT1
IN1
−
OUT2
IN2
−
OUT1
IN2
−
OUT2
V
CONT1
Low
V
CONT2
High
V
CONT3
High
V
CONT4
Low
Control Pin
L
R
Low
High
Low
High
R
L
High
Low
High
Low
R
R
High
Low
Low
High
4
Data Sheet P14268EJ2V0DS00
嵌入式系统
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