CA95C68/18/09
DES DATA CIPHERING PROCESSORS (DCP)
• Encrypts/Decrypts data using National Bureau
of Standards Data Encryption Standard (DES)
• High speed, pin and function compatible
version of industry standard AMD AM9568,
AM9518 and VLSI VM009
• Supports four standard ciphering modes:
Electronic Code Book (ECB), Cipher Block
Chaining (CBC), as well as 1 and 8 bit Cipher
Feedback (CFB)
• Data rates greater than 11 Mbytes per second
(25 MHz) in ECB or CBC modes
• Three separate registers for encryption,
decryption and master keys improve system
security and throughput by eliminating the need
to reload keys frequently
• Fully static CMOS, TTL I/O compatible device,
operates at up to 33MHz
• Low power consumption allows battery back-up
of internal key registers
• Three separate programmable ports (master,
slave and key data)
• Available in 44 pin PLCC and 40 pin PDIP and 44
pin TQFP packages
3
3.2
CA95C68/18/09
The
Tundra Semiconductor Corporation
CA95C68/18/09
DES Data Ciphering Processors (DCPs) implement the
National Bureau of Standards Data Encryption Standard
(DES), FIPS PUB 46 (1-15-1977). The DCPs were designed
to be used in a variety of environments where computer and
communications security is essential.
The DCPs provide a high throughput rate (up to 14 Mbytes
per second) using ECB or CBC modes of operation. The
DCPs provide a unique 1 bit CFB mode as well as the
standard 8 bit mode. Separate ports for key input, clear data
and enciphered data enhance security for your application.
The system communicates with the DCP using commands
entered in the Master Port or through auxiliary control lines.
Once the DCP is set up, data can flow through at high speeds
since input, output and ciphering activities are performed
concurrently. External DMA control can easily be used to
enhance throughput in many system configurations.
The CA95C68 is designed to interface directly to the
iAPX86, 88 CPU bus, and with a minimum of external logic,
to the 2900 and 8051 families of processors. The CA95C18
is designed to interface directly with Z8000, 68000 type bus
interfaces.
The CA95C09 may be configured to behave as either the
CA95C68 or the CA95C18 (see OPTION pin in Table 3-2),
the only difference being the order of the signal names on
the device package.
Table 3-1 : CA95C68/18/09 Data Transfer Rates
Data Transfer Rates
Product
Code
CA95Cxx – 5
CA95Cxx – 10
CA95Cxx – 16
CA95Cxx – 20
CA95Cxx – 25
CA95Cxx-33
ECB or CBC Mode
(Mbytes/s)
CFB-8 Mode
(Mbytes/s)
CFB-1 Mode
(Mbits/s)
System Clock
(MHz)
2.22
4.44
7.10
8.88
11.11
14.81
0.27
0.55
0.88
1.11
1.38
1.85
0.27
0.55
0.88
1.11
1.38
1.85
5
10
16
20
25
33
Tundra Semiconductor Corporation
3-25
CA95C68/18/09
Tundra Semiconductor Corporation
PARITY
BIT
PAR
KEY
OR
CONTROL
AUX7-AUX0
AUXILIARY
PORT
INPUT BUS (8-BITS)
PARITY
CHECK
AUXILIARY
PORT
CONTROL
I/O
AFLG
ASTB
AUXILIARY
PORT
CONTROL
MODE
REGISTER
COMMAND
REGISTER
MASK
REGISTER
INPUT
REGISTER
(64-BITS)
M KEY
REGISTER
(56-BITS)
E KEY
REGISTER
(56-BITS)
D KEY
REGISTER
(56-BITS)
(56-BITS)
MUX/DIRECT
CONTROL
C/K
CLK
CA95C18 CA95C68
MCS
MR/W
MASTER
PORT
CONTROL
I/O
MDS
MAS
MFLG
MCS
MWR
MRD
MALE
MFLG
MASTER
PORT
CONTROL
SFLG
STATUS
REGISTER
OUTPUT
REGISTER
(64-BITS)
IVE
REGISTER
(64-BITS)
IVD
REGISTER
(64-BITS)
SLAVE
PORT
CONTROL
SCS
SDS
SLAVE
PORT
CONTROL
I/O
MASTER
CONTROL
DES ALGORITHM
PROCESSING
UNIT
(64-BITS)
KEY
OR
DATA
MP7-MP0
MASTER
PORT
C BUS (8-BITS)
OUTPUT BUS (8-BITS)
INPUT BUS (8-BITS)
SLAVE
PORT
SP7-SP0
DATA
Figure 3-1 : CA95C68/18/09 Block Diagrams
3-26
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
CA95C68/18/09
VDD
VSS
SP3
SP2
SP1
SP0
SP4
SP5
VSS
SP0
SP1
SP2
SP3
AUX0
AUX1
(BSY) AUX2
(CP) AUX3
AFLG
ASTB
PAR
C/K
CLK
MFLG
MP0
MP1
MP2
MP3
VSS
1
2
3
4
5
6
7
8
9
•
40
39
38
37
36
35
34
33
32
VDD
SP4
SP5
SP6
SP7
AUX4
AUX5 (S/S)
AUX6 (E/D)
AUX7 (K/D)
SFLG
SCS
SDS
MWR
MALE
MRD
MCS
MP4
MP5
MP6
MP7
6
5
4
3
2
1 4 4 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
SP6
SP7
NC
•
AUX0
AUX1
(BSY) AUX2
(CP) AUX3
AFLG
ASTB
PAR
C/K
CLK
MFLG
NC
AUX4
AUX5 (S/S)
AUX6 (E/D)
AUX7 (K/D)
NC
SFLG
SCS
SDS
MWR
MALE
MRD
7
8
9
10 11 12 13 14 15 16 17
10
11
12
13
14
15
16
17
18
19
20
CA95C68
DCP
31
30
29
28
27
26
25
24
23
22
21
CA95C68
DCP
18 19 20 21 22 23 24 25 26 27 28
VSS
MP7
MP6
MCS
MP0
MP1
MP2
MP3
MP5
MP4
Figure 3-2 : CA95C68 40-Pin PDIP
Figure 3-5 : CA95C68 44-Pin PLCC
SP0
SP1
SP2
SP3
AUX0
AUX1
(BSY) AUX2
(CP) AUX3
AFLG
ASTB
PAR
C/K
CLK
MFLG
MP0
MP1
MP2
MP3
VSS
2
3
4
5
6
7
8
9
39
38
37
36
35
34
33
32
SP4
SP5
SP6
SP7
AUX4
AUX5 (S/S)
AUX6 (E/D)
AUX7 (K/D)
SFLG
SCS
SDS
MR/W
MAS
MDS
MCS
MP4
MP5
MP6
MP7
6
5
4
3
NC
VSS
1
•
VDD
VSS
SP3
SP2
SP1
SP0
SP4
SP5
SP6
40
VDD
2
1 4 4 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
SP7
NC
•
AUX0
AUX1
(BSY) AUX2
(CP) AUX3
AFLG
ASTB
PAR
C/K
CLK
MFLG
NC
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
AUX4
AUX5 (S/S)
AUX6 (E/D)
AUX7 (K/D)
NC
SFLG
SCS
SDS
MR/W
MAS
MDS
10
11
12
13
14
15
16
17
18
19
20
CA95C18
DCP
31
30
29
28
27
26
25
24
23
22
21
CA95C18
DCP
MP0
MP1
MP2
MP3
VSS
MP7
MP6
MP5
MP4
SP6
MCS
SP7
Figure 3-3 : CA95C18 40-Pin PDIP
Figure 3-6 : CA95C18 44-Pin PLCC
OPTION
V
OPTION
VDD
VSS
SP3
SP2
SP1
SP0
SP4
SP
3
SP
2
SP
1
SP
0
SP
4
SP
5
SP
6
6
AUX
0
AUX
1
(BSY)AUX
2
(CP)AUX
3
AFLG
V
SS
ASTB
PAR
DCM
CLK
MFLG
7
8
9
10
11
12
13
14
15
16
17
5
4
3
2
1 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
AUX
4
AUX
5
(S/S)
AUX
6
(E/D)
AUX
7
(K/D)
SFLG
V
SS
SP
7
V
44 43 42 41 40 39 38 37 36 35 34
AUX0
AUX1
(BSY)
(CP)
AUX2
AUX3
AFLG
VSS
ASTB
PAR
DCM
CLK
MFLG
SP5
DD
SS
NC
1
2
3
4
5
6
7
8
9
10
11
•
CA95C09
DCP
33
32
31
30
29
28
27
26
25
24
23
AUX4
AUX5(S/S)
AUX6(E/D)
AUX7(K/D)
SFLG
VSS
SCS
SDS
MWR_MR/W
MALE_MAS
MRD_MDS
CA95C09
DCP
SCS
SDS
MWR_MR/W
MALE_MAS
MRD_MDS
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
VSS
MP7
MP6
MP1
MP2
MP3
VDD
MP4
Figure 3-4 : CA95C09 44-Pin PLCC
Figure 3-7 : CA95C09 44-Pin TQFP
Tundra Semiconductor Corporation
MCS
MCS
MP0
MP
1
MP
2
MP
3
MP
7
MP
6
MP
5
MP
0
MP
4
V
DD
V
SS
MP5
3-27
CA95C68/18/09
Tundra Semiconductor Corporation
Table 3-2 : Pin Description
Symbol
CLK
95C68/18
PDIP
14
95C09
PLCC
16
PLCC
15
TQFP
10
TYPE
I
Name and Function
Clock
: An external timing source is input via this pin. The Master and Slave
Port data strobe signals (
MWR
,
MRD
,
SDS
for CA95C68 and
MDS
,
SDS
for CA95C18) must change synchronously with the clock input. In
Direct Control Mode the AUX
5
-S/
S
must also be synchronous. The output
flags for the three ports (
AFLG
,
MFLG
,
SFLG
) will all change
synchronously with the clock.
Control/Key Mode Control
: This input controls the mode of operation of
the DCP. The DCP enters into Multiplexed Control Mode when a low input is
placed on the C/
K
pin, enabling programmed access to internal registers
through the Master Port and enabling input of keys through the Auxiliary
Port. In Direct Control Mode (C/
K
HIGH), several of the Auxiliary Port pins
become direct control/status signals which can be driven/sensed by high-
speed controller logic, and access to internal registers through the Master
Port is limited to the Input and Output Registers.
Direct Control Mode
: (
For CA95C09
) This input functions identical to the
C/
K
input. (See C/
K
pin description).
Master Port Bus
: These eight bi-directional signals are used to input and
output data, as well as specify the internal register addresses in Multiplexed
Control Mode. The Master Port provides software access to the Status,
Command, Mode, Mask, Input and Output Registers. For the CA95C68, the
tri-state Master Port outputs will be enabled only when the Master Port is
selected by Master Port Chip Select (
MCS
) LOW, and when Master Port
Read (
MRD
) is strobed LOW. For the CA95C18, the Master Port outputs
are enabled when selected by
MCS
, and when MR/
W
is HIGH and
MDS
is LOW. MP
0
is the low-order bit. Data and key information are entered into
this port with the most significant byte first.
Master Port Chip Select
: This active LOW input signal is used to select the
Master Port. In Multiplexed Control Mode (C/
K
LOW), the level on
MCS
is
latched internally on the falling edge of Master Port Address Latch Enable
(MALE). This latched level is maintained as long as MALE is LOW; when
MALE is HIGH, the latch becomes transparent and the internal signal will
follow the
MCS
input. No latching of
MCS
occurs in Direct Control Mode
(C/
K
HIGH). The level on
MCS
is passed directly to the internal select
circuitry regardless of the state of Master Port Address Latch Enable
(MALE).
C/
K
13
14
–
–
I
DCM
–
–
15
9
I
MP
7
–
MP
0
21-24
19-16
23-26
21-18
24-27
21-18
18-21
15-12
I/O
MCS
25
27
28
22
I
3-28
Tundra Semiconductor Corporation
Tundra Semiconductor Corporation
Table 3-2 : Pin Description
Cont'd
Symbol
MALE
CA95C68/18/09
95C68/18
PDIP
27
95C09
PLCC
–
PLCC
30
TQFP
–
TYPE
I
Name and Function
Master Port Address Latch Enable
: (
For CA95C68
) In Multiplexed Control
Mode (C/
K
LOW), an active HIGH signal on this pin indicates the presence of
valid address and chip select information at the Master Port. This information
will be latched internally on the falling edge of MALE. When C/
K
is HIGH
(Direct Control Mode), MALE has no affect on DCP operation.
Master Port Read
: (
For CA95C68
) This active LOW input is used with a
valid
MCS
to indicate that data is to be output on the Master Port bus.
Master Port Read (
MRD
) and Master Port Write (
MWR
) are normally
mutually exclusive; if both become active simultaneously, the DCP is reset to
ECB Mode and all flags go inactive.
Master Port Write
: (
For CA95C68
) This active low input signal indicates to
the DCP that valid data is present on MP
7
-MP
0
for an input operation. The
rising edge of
MWR
latches the data into the selected internal register. If
MWR
and
MRD
both go LOW simultaneously, the DCP is reset.
Master Port Address Strobe
: (
For CA95C18
) In Multiplexed Control Mode
(C/
K
HIGH), a LOW on
MAS
indicates the presence of a valid chip select
signal and address information. This information will be latched on the rising
edge of
MAS
. In Direct Control Mode,
MAS
has no affect on the DCP
operation. The DCP will be reset if
MAS
and
MDS
both go low
simultaneously.
Master Port Data Strobe
: (
For CA95C18
) This active low input is used in
conjunction with a valid Master Port Chip Select (
MCS
) to indicate that
valid data is present on the MP
7
-MP
0
bus for an input operation or that data
is to be placed on the Master Port Bus during output.
MDS
and
MAS
are
mutually exclusive; if they both go active simultaneously, the DCP is reset to
ECB mode and all flags go inactive.
Master Port Read/Write
: (
For CA95C18
) This input signal indicates to the
DCP whether the current Master Port operation is a read (HIGH) where data
is transferred from the device, or a write (LOW) where data is stored to an
internal register. MR/
W
is not latched internally and must be held stable while
MDS
is LOW.
MRD
26
29
–
–
I
MWR
28
31
–
–
I
MAS
27
30
–
–
I
MDS
26
29
–
–
I
MR/
W
28
31
–
–
I
Tundra Semiconductor Corporation
3-29
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