Data are valid at +25°C, unless otherwise specified.
Parameter
Input
Nominal input voltage
Permanent input
voltage range (Ui)
Input surge withstand
Undervoltage lock-out
(UVLO)
Overvoltage lock-out
(OVLO)
Start up time
Reflected ripple current
Input current in short
circuit
mode (Average)
No load input current
Input current in inhibit
mode
Output
Conditions
Limit or
typical
Nominal
Min. - Max.
Maximum
Nominal
Nominal
Nominal
Nominal
Maximum
Maximum
Typical
Maximum
Maximum
Units
Hi-Rel
Grade
Single Output MGDS-150
150 - H
24
9 - 45
50/1
8,5
7,5
45
46
30
200
1
30
15
150 - O
28
16 - 80
100/1
15,5
14,5
80
81
30
500
1
30
15
Full temperature range
Full temperature range
Above OVLO converter
Turns - off
Turn-on voltage
Turn-off voltage
Turn-on voltage
Turn-off voltage
Ui nominal
Nominal output
Full load : resistive
Ui nominal, full load
BW = 20MHz
Ui nominal
Short-circuit
Ui nominal
No load
Ui nominal
Inhibit
VDC
VDC
VDC/min.
VDC
VDC
VDC
VDC
ms
mApp
A
mA
mA
Output voltage *
Ui min. to max.
Nominal
Nominal
Nominal
Nominal
Nominal
Nominal
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Maximum
Typical
Typical
Typical
Typical
Maximum
Minimum
Maximum
Typical
VDC
VDC
VDC
VDC
VDC
VDC
%
W
A
A
A
A
A
A
mVpp
mVpp
mVpp
mVpp
%
%
%
%
3,3
5
12
15
24
28
+/- 2
100 to 150
30
25
12,5
10
6,25
5,35
50
100
150
250
+/- 1
10 **
110
3,3
5
12
15
24
28
+/- 2
100 to 150
30
30
12,5
10
6,25
5,35
50
100
150
250
+/- 1
10 **
110
4
Set Point accuracy *
Output power **
Output current **
3,3V output
5V output
12V output
15V output
24V output
28V output
Ripple output voltage ***
3,3V and 5V output
12V output
15V output
24V and 28V output
Output regulation *
(Line + load + thermal)
Output Voltage Trim
Efficiency
Ambient temperature : +25°c
Ui nominal, 75% load
At 105°c baseplate
Ui min. to max.
Full temperature range
Ui min. to max.
Ui nominal
Full load
BW = 20MHz
Ui min. to max.
0% to full load
As function of output voltage
Ui nominal
Full load
see curves page 5 and 6
Note * : These performances are measured with the sense line connected..
Note ** : It is recommended to mount the converter on a heatsink for this test, see section 10-3 and 10-9 for further details.
Note *** : The ripple output voltage is the periodic AC component imposed on the output voltage, an aperiodic and random component (noise) has also to be considered.
This noise can be reduced by adding 4 external decoupling capacitors connected between inputs and case and between outputs and case. These capacitance should
be layed-out as close as possible from the converter. Please refer to page 8 for more details.
FPGA/CPLD
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