74LVC1G58-Q100
Low-power configurable multiple function gate
Rev. 1 — 10 June 2014
Product data sheet
1. General description
The 74LVC1G58-Q100 provides configurable multiple functions. The output state is
determined by eight patterns of 3-bit input. The user can choose the logic functions AND,
OR, NAND, NOR, XOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
All inputs (A, B and C) are Schmitt trigger inputs. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant input/output for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V).
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
24
mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
NXP Semiconductors
74LVC1G58-Q100
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74LVC1G58GW-Q100
40 C
to +125
C
74LVC1G58GV-Q100
40 C
to +125
C
SC-88
TSOP6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic surface-mounted package (TSOP6); 6 leads SOT457
4. Marking
Table 2.
Marking
Marking code
[1]
YK
V58
Type number
74LVC1G58GW-Q100
74LVC1G58GV-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
3
4
B
1
Y
A
C
6
001aab687
Fig 1.
Logic symbol
6. Pinning information
6.1 Pinning
Fig 2.
Pin configuration SOT363 and SOT457
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
2 of 17
NXP Semiconductors
74LVC1G58-Q100
Low-power configurable multiple function gate
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
7. Functional description
Table 4.
Inputs
C
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
H
L
H
H
H
L
L
H = HIGH voltage level; L = LOW voltage level
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 3
see
Figure 6
see
Figure 4
and
5
see
Figure 4
and
5
see
Figure 6
see
Figure 3
see
Figure 7
see
Figure 8
see
Figure 9
Logic function
2-input NAND
2-input NAND with both inputs inverted
2-input AND with inverted input
2-input NOR with inverted input
2-input OR
2-input OR with both inputs inverted
2-input XOR
Buffer
Inverter
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
3 of 17
NXP Semiconductors
74LVC1G58-Q100
Low-power configurable multiple function gate
V
CC
B
C
Y
B
1
2
B
C
Y
3
6
5
4
Y
B
C
Y
C
B
C
Y
B
1
2
3
6
5
4
Y
C
V
CC
001aab688
001aab689
Fig 3.
2-input NAND gate or 2-input OR with both
inputs inverted
Fig 4.
2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
V
CC
V
CC
A
C
Y
1
2
A
C
Y
A
3
6
5
4
Y
A
C
Y
A
C
A
C
Y
1
2
3
6
5
4
Y
C
001aab690
001aab691
Fig 5.
2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
Fig 6.
2-input OR gate or 2-input NAND gate with
both inputs inverted
V
CC
V
CC
B
B
C
Y
1
2
3
6
5
4
Y
C
A
Y
A
1
2
3
6
5
4
Y
001aab692
001aab693
Fig 7.
2-input XOR gate
Fig 8.
Buffer
V
CC
B
B
Y
1
2
3
6
5
4
Y
001aab694
Fig 9.
Inverter
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
4 of 17
NXP Semiconductors
74LVC1G58-Q100
Low-power configurable multiple function gate
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[1][2]
[1][2]
Max
+6.5
-
+6.5
50
+6.5
+6.5
50
100
-
+150
250
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
Active mode
Power-down mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
For SC-88 and SC-74 packages: above 87.5
C
the value of P
tot
derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
Recommended operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
1.65
0
0
0
40
Typ
-
-
-
-
-
Max
5.5
5.5
V
CC
5.5
+125
Unit
V
V
V
V
C
74LVC1G58_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 1 — 10 June 2014
5 of 17
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