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74LVC07A-Q100
Hex buffer with open-drain outputs
Rev. 1 — 1 October 2012
Product data sheet
1. General description
The 74LVC07A-Q100 provides six non-inverting buffers. The outputs are open-drain and
can be connected to other open-drain outputs to implement active-LOW wired-OR or
active-HIGH wired-AND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
NXP Semiconductors
74LVC07A-Q100
Hex buffer with open-drain outputs
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC07AD-Q100
40 C
to +125
C
Name
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
Type number
74LVC07APW-Q100
40 C
to +125
C
74LVC07ABQ-Q100
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
1
1A
1Y 2
1A
1
1
2
1Y
3
2A
2Y 4
2A
5
3A
3Y 6
3
1
4
2Y
3A
9
4A
4Y 8
5
1
6
3Y
4A
11
5A
5Y 10
9
1
8
4Y
5A
13
6A
6Y 12
11
1
10
5Y
A
Y
6A
mna535
13
1
mna534
12
6Y
GND
mna533
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram for one gate
74LVC07A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 October 2012
2 of 15
NXP Semiconductors
74LVC07A-Q100
Hex buffer with open-drain outputs
5. Pinning information
5.1 Pinning
74LVC07A-Q100
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
aaa-005041
/9&$4
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
8
4A
4Y
WHUPLQDO
LQGH[ DUHD
<
$
<
$
<
*1'
<
*1'
9
&&
$
<
$
<
$
$
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 4.
Pin configuration for SO14 and TSSOP14
Fig 5.
Pin configuration for DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A, 2A, 3A, 4A, 5A, 6A
1Y, 2Y, 3Y, 4Y, 5Y, 6Y
GND
V
CC
Pin description
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
H
[1]
Function selection
[1]
Output
nY
L
Z
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
74LVC07A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 October 2012
3 of 15
NXP Semiconductors
74LVC07A-Q100
Hex buffer with open-drain outputs
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
P
tot
T
stg
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
total power dissipation
storage temperature
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[2]
[2]
Max
+6.5
-
+6.5
-
+6.5
+6.5
50
100
-
500
+150
Unit
V
mA
V
mA
V
V
mA
mA
mA
mW
C
V
O
< 0 V
active mode
high-impedance mode
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
T
amb
=
40 C
to +125
C
[3]
-
65
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO14 packages: above 70
C
derate linearly with 8 mW/K.
For TSSOP14 packages: above 60
C
derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60
C
derates linearly with 4.5 mW/K.
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall
rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
active mode
high-impedance mode
Conditions
Min
1.65
1.2
0
0
0
40
0
0
Typ
-
-
-
-
-
-
-
-
Max
5.5
-
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
74LVC07A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 1 October 2012
4 of 15
NXP MCU
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