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Datasheet> 器件分类 > 逻辑> 逻辑> 74AUP1G97GW
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74AUP1G97GW

产品描述Logic Circuit, CMOS, PDSO6
产品类别逻辑    逻辑   
文件大小315KB，共23页
制造商Nexperia
官网地址https://www.nexperia.com
标准
下载文档 详细参数 选型对比 全文预览

74AUP1G97GW概述

Logic Circuit, CMOS, PDSO6

74AUP1G97GW规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Nexperia
包装说明SC-88, 6 PIN
Reach Compliance Codecompliant
系列AUP/ULP/V
JESD-30 代码R-PDSO-G6
JESD-609代码e3
长度2 mm
逻辑集成电路类型LOGIC CIRCUIT
湿度敏感等级1
功能数量1
端子数量6
最高工作温度125 °C
最低工作温度-40 °C
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）260
认证状态Not Qualified
座面最大高度1.1 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)0.8 V
标称供电电压 (Vsup)1.1 V
表面贴装YES
技术CMOS
温度等级AUTOMOTIVE
端子面层Tin (Sn)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间30
宽度1.25 mm

74AUP1G97GW文档预览

74AUP1G97
Low-power configurable multiple function gate
Rev. 9 — 17 September 2015
Product data sheet
1. General description
The 74AUP1G97 provides configurable multiple functions. The output state is determined
by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR,
NAND, NOR, inverter and buffer. All inputs can be connected to V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G97 has Schmitt trigger inputs making it capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
T+
and the negative voltage V
T
is defined as the input
hysteresis voltage V
H
.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP1G97GW
74AUP1G97GM
74AUP1G97GF
74AUP1G97GN
74AUP1G97GS
74AUP1G97GX
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SC-88
XSON6
XSON6
XSON6
XSON6
X2SON6
Description
plastic surface-mounted package; 6 leads
Version
SOT363
Type number
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1
1.45
0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1
1
0.5 mm
extremely thin small outline package; no leads;
6 terminals; body 0.9
1.0
0.35 mm
extremely thin small outline package; no leads;
6 terminals; body 1.0
1.0
0.35 mm
plastic thermal extremely thin small outline package;
no leads; 6 terminals; body 1
0.8
0.35 mm
SOT1115
SOT1202
SOT1255
4. Marking
Table 2.
Marking
Marking code
[1]
aV
aV
aV
aV
aV
aV
Type number
74AUP1G97GW
74AUP1G97GM
74AUP1G97GF
74AUP1G97GN
74AUP1G97GS
74AUP1G97GX
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 17 September 2015
2 of 23
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
6. Pinning information
6.1 Pinning
Fig 2.
Pin configuration SOT363
Fig 3.
Pin configuration SOT886
Fig 4.
Pin configuration SOT891, SOT1115 and
SOT1202
Fig 5.
Pin configuration SOT1255 (X2SON6)
6.2 Pin description
Table 3.
Symbol
B
GND
A
Y
V
CC
C
Pin description
Pin
1
2
3
4
5
6
Description
data input
ground (0 V)
data input
data output
supply voltage
data input
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 17 September 2015
3 of 23
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
7. Functional description
Table 4.
Input
C
L
L
L
L
H
H
H
H
[1]
H = HIGH voltage level;
L = LOW voltage level.
Function table
[1]
Output
B
L
L
H
H
L
L
H
H
A
L
H
L
H
L
H
L
H
Y
L
L
H
H
L
H
L
H
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 6
see
Figure 7
see
Figure 8
see
Figure 8
see
Figure 9
see
Figure 9
see
Figure 10
see
Figure 11
see
Figure 12
Logic function
2-input MUX
2-input AND
2-input OR with one input inverted
2-input NAND with one input inverted
2-input AND with one input inverted
2-input NOR with one input inverted
2-input OR
Inverter
Buffer
Fig 6.
2-input MUX
Fig 7.
2-input AND gate
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 17 September 2015
4 of 23
NXP Semiconductors
74AUP1G97
Low-power configurable multiple function gate
Fig 8.
2-input NAND gate with input A inverted or
2-input OR gate with input C inverted
Fig 9.
2-input NOR gate with input B inverted or
2-input AND gate with input C inverted
Fig 10. 2-input OR gate
Fig 11. Inverter
Fig 12. Buffer
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
V
O
< 0 V
Active mode and Power-down
mode
V
O
= 0 V to V
CC
[1]
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
0.5
-
-
50
65
Max
+4.6
-
+4.6
-
+4.6
20
50
-
+150
Unit
V
mA
V
mA
V
mA
mA
mA
C
74AUP1G97
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 9 — 17 September 2015
5 of 23
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74AUP1G97GW相似产品对比

74AUP1G97GW 74AUP1G97GX 74AUP1G97GF 74AUP1G97GM 74AUP1G97GN 74AUP1G97GS
描述 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6
是否Rohs认证 符合 符合 符合 符合 符合 符合
厂商名称 Nexperia Nexperia Nexperia Nexperia Nexperia Nexperia
包装说明 SC-88, 6 PIN X2SON-6 VSON, VSON, XSON-6 VSON,
Reach Compliance Code compliant compliant compliant compliant compliant compliant
系列 AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V
JESD-30 代码 R-PDSO-G6 R-PBCC-B6 S-PDSO-N6 R-PDSO-N6 R-PDSO-N6 S-PDSO-N6
JESD-609代码 e3 e4 e3 e3 e3 e3
长度 2 mm 1 mm 1 mm 1.45 mm 1 mm 1 mm
逻辑集成电路类型 LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT
湿度敏感等级 1 1 1 1 1 1
功能数量 1 1 1 1 1 1
端子数量 6 6 6 6 6 6
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSSOP HVBCC VSON VSON SON VSON
封装形状 RECTANGULAR RECTANGULAR SQUARE RECTANGULAR RECTANGULAR SQUARE
封装形式 SMALL OUTLINE, THIN PROFILE, SHRINK PITCH CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度（摄氏度） 260 NOT SPECIFIED 260 260 260 260
座面最大高度 1.1 mm 0.35 mm 0.5 mm 0.5 mm 0.35 mm 0.35 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V 0.8 V
标称供电电压 (Vsup) 1.1 V 1.1 V 1.1 V 1.1 V 1.1 V 1.1 V
表面贴装 YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
端子面层 Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au) Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn)
端子形式 GULL WING BUTT NO LEAD NO LEAD NO LEAD NO LEAD
端子位置 DUAL BOTTOM DUAL DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 NOT SPECIFIED 30 30 30 30
宽度 1.25 mm 0.8 mm 1 mm 1 mm 0.9 mm 1 mm
认证状态 Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified
端子节距 0.65 mm - 0.35 mm 0.5 mm 0.3 mm 0.35 mm

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