74AUP1G74-Q100
Low-power D-type flip-flop with set and reset; positive-edge
trigger
Rev. 1 — 27 May 2015
Product data sheet
1. General description
The 74AUP1G74-Q100 provides a low-power, low-voltage single positive-edge triggered
D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs and
complementary Q and Q outputs. The SD and RD are asynchronous active LOW inputs
and operate independently of the clock input. Information on the data input is transferred
to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be
stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire V
CC
range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V
HBM JESD22-A114F Class 3A. Exceeds 5000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
NXP Semiconductors
74AUP1G74-Q100
Low-power D-type flip-flop with set and reset; positive-edge trigger
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74AUP1G74DC-Q100
40 C
to +125
C
Description
Version
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
Type number
4. Marking
Table 2.
Marking codes
Marking code
[1]
p74
Type number
74AUP1G74DC-Q100
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74AUP1G74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 27 May 2015
2 of 21
NXP Semiconductors
74AUP1G74-Q100
Low-power D-type flip-flop with set and reset; positive-edge trigger
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
Fig 4.
Pin configuration SOT765-1
6.2 Pin description
Table 3.
Symbol
CP
D
Q
GND
Q
RD
SD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
Description
clock input
data input
complement output
ground (0 V)
true output
asynchronous reset input (active LOW)
asynchronous set input (active LOW)
supply voltage
74AUP1G74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 27 May 2015
3 of 21
NXP Semiconductors
74AUP1G74-Q100
Low-power D-type flip-flop with set and reset; positive-edge trigger
7. Functional description
Table 4.
Input
SD
L
H
L
[1]
Function table for asynchronous operation
[1]
Output
RD
H
L
L
CP
X
X
X
D
X
X
X
Q
H
L
H
Q
L
H
H
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Table 5.
Input
SD
H
H
[1]
Function table for synchronous operation
[1]
Output
RD
H
H
CP
D
L
H
Q
n+1
L
H
Q
n+1
H
L
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH CP transition;
Q
n+1
= state after the next LOW-to-HIGH CP transition.
8. Limiting values
Table 6.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
50
[1]
Max
+4.6
-
+4.6
-
+4.6
20
+50
-
+150
250
Unit
V
mA
V
mA
V
mA
mA
mA
C
mW
V
O
< 0 V
Active mode and Power-down mode
V
O
= 0 V to V
CC
0.5
-
-
50
65
T
amb
=
40 C
to +125
C
[2]
-
The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For VSSOP8 packages: above 110
C
the value of P
tot
derates linearly with 8.0 mW/K.
74AUP1G74_Q100
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 27 May 2015
4 of 21
NXP Semiconductors
74AUP1G74-Q100
Low-power D-type flip-flop with set and reset; positive-edge trigger
9. Recommended operating conditions
Table 7.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Operating conditions
Parameter
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 0.8 V to 3.6 V
Active mode
Power-down mode; V
CC
= 0 V
Conditions
Min
0.8
0
0
0
40
-
Max
3.6
3.6
V
CC
3.6
+125
200
Unit
V
V
V
V
C
ns/V
10. Static characteristics
Table 8.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
T
amb
= 25
C
V
IH
HIGH-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
IL
LOW-level input voltage
V
CC
= 0.8 V
V
CC
= 0.9 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
V
OH
HIGH-level output voltage
V
I
= V
IH
or V
IL
I
O
=
20 A;
V
CC
= 0.8 V to 3.6 V
I
O
=
1.1
mA; V
CC
= 1.1 V
I
O
=
1.7
mA; V
CC
= 1.4 V
I
O
=
1.9
mA; V
CC
= 1.65 V
I
O
=
2.3
mA; V
CC
= 2.3 V
I
O
=
3.1
mA; V
CC
= 2.3 V
I
O
=
2.7
mA; V
CC
= 3.0 V
I
O
=
4.0
mA; V
CC
= 3.0 V
V
OL
LOW-level output voltage
V
I
= V
IH
or V
IL
I
O
= 20
A;
V
CC
= 0.8 V to 3.6 V
I
O
= 1.1 mA; V
CC
= 1.1 V
I
O
= 1.7 mA; V
CC
= 1.4 V
I
O
= 1.9 mA; V
CC
= 1.65 V
I
O
= 2.3 mA; V
CC
= 2.3 V
I
O
= 3.1 mA; V
CC
= 2.3 V
I
O
= 2.7 mA; V
CC
= 3.0 V
I
O
= 4.0 mA; V
CC
= 3.0 V
74AUP1G74_Q100
All information provided in this document is subject to legal disclaimers.
Conditions
Min
0.70
V
CC
0.65
V
CC
1.6
2.0
-
-
-
-
V
CC
0.1
0.75
V
CC
1.11
1.32
2.05
1.9
2.72
2.6
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
Unit
V
V
V
V
0.30
V
CC
V
0.35
V
CC
V
0.7
0.9
-
-
-
-
-
-
-
-
0.1
0.31
0.31
0.31
0.44
0.31
0.44
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
0.3
V
CC
V
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 1 — 27 May 2015
5 of 21
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