74ABT00
Quad 2-input NAND gate
Rev. 3 — 11 August 2016
Product data sheet
1. General description
The 74ABT00 high-performance BiCMOS device combines low static and dynamic power
dissipation with high speed and high output drive.
The 74ABT00 is a quad 2-input NAND gate.
2. Features and benefits
Latch-up protection exceeds 500 mA per JESD78B class II level A
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74ABT00D
74ABT00DB
74ABT00PW
40 C
to +85
C
40 C
to +85
C
40 C
to +85
C
SO14
SSOP14
TSSOP14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT337-1
SOT402-1
Type number
NXP Semiconductors
74ABT00
Quad 2-input NAND gate
4. Functional diagram
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
Fig 4.
Pin configuration for SO14
Fig 5.
Pin configuration for SSOP14 and TSSOP14
5.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
74ABT00
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 11 August 2016
2 of 12
NXP Semiconductors
74ABT00
Quad 2-input NAND gate
6. Functional description
Table 3.
Input
nA
L
X
H
[1]
Function table
[1]
Output
nB
X
L
H
nY
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
j
T
stg
[1]
[2]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
junction temperature
storage temperature
Conditions
[1]
Min
0.5
1.2
0.5
18
50
-
[2]
Max
+7.0
+7.0
+5.5
-
-
40
150
+150
Unit
V
V
V
mA
mA
mA
C
C
output HIGH or LOW
V
I
< 0 V
V
O
< 0 V
output in LOW-state
[1]
-
65
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150
C.
8. Recommended operating conditions
Table 5.
Operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
t/V
T
amb
Parameter
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise and fall rate
ambient temperature
in free air
Conditions
Min
4.5
0
2.0
-
15
-
0
40
Typ
-
-
-
-
-
-
-
-
Max
5.5
V
CC
-
0.8
-
20
5
+85
Unit
V
V
V
V
mA
mA
ns/V
C
74ABT00
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 11 August 2016
3 of 12
NXP Semiconductors
74ABT00
Quad 2-input NAND gate
9. Static characteristics
Table 6.
Symbol
V
IK
V
OH
V
OL
I
I
I
OFF
I
CEX
I
O
I
CC
I
CC
Static characteristics
Parameter
Conditions
Min
input clamping voltage V
CC
= 4.5 V; I
IK
=
18
mA
HIGH-level output
voltage
LOW-level output
voltage
input leakage current
power-off leakage
current
output high leakage
current
output current
supply current
additional supply
current
input capacitance
V
CC
= 4.5 V; I
OH
=
15
mA;
V
I
= V
IL
or V
IH
V
CC
= 4.5 V; I
OL
= 20 mA;
V
I
= V
IL
or V
IH
V
CC
= 5.5 V; V
I
= GND or 5.5 V
V
CC
= 0 V; V
I
or V
O
4.5 V
HIGH-state; V
O
= 5.5 V;
V
CC
= 5.5 V; V
I
= GND or V
CC
V
CC
= 5.5 V; V
O
= 2.5 V
V
CC
= 5.5 V; V
I
= GND or V
CC
per input pin; V
CC
= 5.5 V;
one input at 3.4 V;
other inputs at V
CC
or GND
V
I
= 0 V or V
CC
[2]
[1]
25
C
Typ
0.9
2.9
0.35
Max
-
-
0.5
1.2
2.5
-
-
-
-
50
-
-
40 C
to +85
C
Unit
Min
1.2
2.5
-
-
-
-
50
-
-
Max
-
-
0.5
1.0
100
50
180
50
500
V
V
V
A
A
A
mA
A
A
0.01 1.0
5.0
5.0
75
2
0.25
100
50
180
50
500
C
I
[1]
[2]
-
3
-
-
-
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see
Figure 7.
Symbol Parameter
Conditions
25
C;
V
CC
= 5.0 V
Min
t
PLH
t
PHL
t
sk(o)
[1]
40 C
to +85
C;
V
CC
= 5.0 V
0.5 V
Min
1.0
1.0
-
Max
4.1
3.4
0.5
Unit
Typ
2.5
2.0
0.4
Max
3.6
2.8
0.5
LOW to HIGH
propagation delay
HIGH to LOW
propagation delay
output skew time
nA, nB to nY; see
Figure 6
nA, nB to nY; see
Figure 6
[1]
1.0
1.0
-
ns
ns
ns
Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
74ABT00
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 11 August 2016
4 of 12
NXP Semiconductors
74ABT00
Quad 2-input NAND gate
11. Waveforms
V
M
= 1.5 V
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 6.
Propagation delay input (nA, nB) to output (nY) and output skew time
a. Input pulse definition
Test data is given in
Table 8.
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
b. Test circuit
R
T
= Termination resistance should be equal to output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 7.
Table 8.
Input
V
I
3.0 V
Test circuit for measuring switching times
Test data
Load
f
i
1 MHz
t
W
500 ns
t
r
, t
f
2.5 ns
C
L
50 pF
R
L
500
V
EXT
t
PHL
, t
PLH
open
74ABT00
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 3 — 11 August 2016
5 of 12
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