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74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 4 — 24 February 2016
Product data sheet
1. General description
The 74HC377; 74HCT377 is an octal positive-edge triggered D-type flip-flop. The device
features clock (CP) and data enable (E) inputs. When E is LOW, the outputs Qn assume
the state of their corresponding Dn inputs that meet the set-up and hold time requirements
on the LOW-to-HIGH clock (CP) transition. Input E must be stable one set-up time prior to
the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that
enable the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
2. Features and benefits
Common clock and master reset
Eight positive edge-triggered D-type flip-flops
Complies with JEDEC standard no. 7A
Input levels:
For 74HC377: CMOS level
For 74HCT377: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V.
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC377D
74HCT377D
74HC377DB
74HCT377DB
74HC377PW
74HCT377PW
40 C
to +85
C
40 C
to +85
C
SSOP20
plastic shrink small outline package; 20 leads; body width
5.3 mm
SOT339-1
SOT360-1
40 C
to +85
C
SO20
Description
plastic small outline package; 20 leads; body width 7.5 mm
Version
SOT163-1
Type number
TSSOP20 plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
NXP Semiconductors
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
4. Functional diagram
Fig 1.
Functional diagram
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
74HC_HCT377
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 24 February 2016
2 of 18
NXP Semiconductors
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Fig 4.
Logic diagram
74HC_HCT377
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 24 February 2016
3 of 18
NXP Semiconductors
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
5. Pinning information
5.1 Pinning
Fig 5.
Pin configuration
5.2 Pin description
Table 2.
Symbol
E
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
D0, D1, D2, D3, D4, D5, D6, D7
GND
CP
V
CC
Pin description
Pin
1
2, 5, 6, 9, 12, 15, 16, 19
3, 4, 7, 8, 13, 14, 17, 18
10
11
20
Description
data enable input (active LOW)
flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
supply voltage
6. Functional description
Table 3.
Function table
[1]
Inputs
CP
load “1”
load “0”
hold (do nothing)
-
X
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Operating modes
Outputs
E
l
l
h
H
Dn
h
l
X
X
Qn
H
L
no change
no change
74HC_HCT377
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 4 — 24 February 2016
4 of 18
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