words of 8 bits each when it is tied to ground. The
instruction set includes read, write, and write
enable/disable functions. The data out pin (DO)
indicates the status of the device during the
self-timed non-volatile programming cycle.
The self-timed write cycle includes an automatic
erase-before-write capability. Only when the chip is
in the WRITE ENABLE state and proper VCC
operation range is the WRITE instruction accepted
and thus to protect against inadvertent writes. Data
is written in 16 bits per write instruction into the
selected register. If Chip Select (CS) is brought
HIGH after initiation of the write cycle, the Data
Output (DO) pin will indicate the READY/BUSY
status of the chip.
The AM93LC56 is available in space-saving 8-lead
PDIP, 8-lead SOP and rotated 8-lead SOP package.
Connection Diagram
Pin Assignments
Name
CS
SK
DI
DO
GND
VCC
NC
ORG
Description
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
No Connection
Internal Organization
CS
SK
DI
DO
1
2
3
4
8
7
6
5
VCC
NC
ORG
GND
NC
VCC
CS
SK
1
2
3
4
8
7
6
5
ORG
GND
DO
DI
PDIP-8L / SOP-8L
Rotated SOP-8L
Ordering Information
AM 93 L C 56 X XX
X
Operating Voltage
LC : 2.7~5.5V,CMOS
Type
56: 2K
Temp. grade
o
o
Blank : 0 C ~
+
70 C
o
o
I :
−
40 C ~
+
85 C
V :
−
40 o C ~
+
125 o C
Package
Packing
S : SOP-8L
Blank : Tube
GS8: SOP-8L,G type A : Taping
N : PDIP-8L
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev.A1 Oct 20, 2003
1/10
ATC
2048-bits Serial Electrically Erasable PROM
Block Diagrams
DI
INSTRUCTION
REGISTER
(10 BITS)
DATA
REGISTER
DUMMY BIT
AM93LC56
DO
R/W AMPS
CS
INSTRUCTION
DECODE
CONTROL
AND
CLOCK
GENERATION
ADDRESS
REGISTER
DECODER
EEPROM
ARRAY
(128 X 16)
OR
(256 X 8)
V
CC
RANGE
DETECTOR
SK
WRITE ENABLE
HIGH VOLTAGE
GENERATOR
ORG
Absolute Maximum Ratings
Characteristics
Storage Temperature
Voltage with Respect to Ground
Symbol
T
S
Values
-65 to + 125
-0.3 to + 6.5
Unit
°C
V
NOTE:These
are STRESS rating only. Appropriate conditions for operating these devices given elsewhere may permanently damage the
part. Prolonged exposure to maximum ratings may affect device reliability.
Operating Conditions
Temperature under bias
AM93LC56
AM93LC56I
AM93LC56V
Values
0 to + 70
-40 to + 85
-40 to +125
Unit
°C
°C
°C
DC Electrical Characteristics
Parameter
Operating current**
Standby current
Input leakage
Output leakage
Input low voltage**
Input high voltage**
Output low voltage
Output high voltage
Output low voltage
Output high voltage
Symbol
I
CC
I
SB
I
IL
I
OL
V
IL
V
IH
V
OL1
V
OH1
V
OL2
(Vcc =2.7~5.5V, Ta = 25
o
C , unless otherwise noted)
Min
Max
Units
3
mA
10
µA
1
µA
1
µA
0.15 V
CC
V
0.8
V
CC
+0.2
V
V
CC
+0.2
0.4
V
V
0.2
V
V
Conditions
CS=V
IH
, SK=1MHz CMOS input levels
CS=DI=SK=0V
V
IN
= 0V to V
CC(CS,SK,DI)
V
OUT
= 0V to V
CC
, CS=0V
V
CC
= 3V + 10%
V
CC
= 5V + 10%
V
CC
= 3V + 10%
V
CC
= 5V + 10%
I
OL
= 2.1mA TTL, V
CC
=5V + 10%
I
OH
= -400uA TTL, V
CC
=5V + 10%
I
OL
= 10uA CMOS
I
OH
= -10uA CMOS
-1
-1
-0.1
-0.1
0.8 V
CC
2
2.4
V
CC
-0.2
Note **:
I
CC
, V
IL
min and V
IH
max are for reference only and are not tested
Anachip Corp.
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2/10
Rev. A1 Oct 20, 2003
ATC
2048-bits Serial Electrically Erasable PROM
AM93LC56
AM93LC56
Min
Max
0
1
250
250
250
50
100
0
100
500
500
500
100
10
1M
AC Electrical Characteristics
(Vcc = 2.7V ~ 5.5V, Ta = 25
o
C , unless otherwise noted)
Parameter
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to "1"
Output Delay to "0"
CS to Status Valid
CS to DO in 3-state
Write Cycle Time
5V, 25ºC, Page Mode
Symbol
F
SK
T
SKH
T
SKL
T
CS
T
CSS
T
DIS
T
cSH
T
DIH
T
pD1
T
pD0
T
SV
T
dF
T
wP
Endurance**
Conditions
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
write cycles
Relative to SK
Relative to SK
Relative to SK
Relative to SK
AC Test
AC Test
AC Test CL = 100pF
CS = VIL
Note** :
The parameter is characterized and isn’t 100% tested.
1.247V
(1 TTL Gate Load)
632 ohm
DO
100PF
FIGURE 1. AC TEST CONDITIONS
Instruction Set
Instruction
READ
WEN (Write Enable)
WRITE
WRALL (Write All Registers)
WDS (Write Disable)
ERASE
ERAL (Erase All Registers)
Start
Bit
1
1
1
1
1
1
1
OP
Code
10
00
01
00
00
11
00
Address
×
8
A
7
- A
0
11 XXXXXX
A
7
- A
0
01XXXXXX
00 XXXXXX
A
7
- A
0
10 XXXXXX
×
16
A
6
- A
0
11XXXXX
A
6
- A
0
01XXXXX
00XXXXX
A
6
- A
0
10XXXXX
Input Data
×
8
×
16
D
7
– D
0
D
7
– D
0
D
15
- D
0
D
15
- D
0
Anachip Corp.
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3/10
Rev. A1 Oct 20, 2003
ATC
2048-bits Serial Electrically Erasable PROM
Pin Capacitance **
(Ta=25°C , f=1MH
z
)
Symbol
C
OUT
C
IN
Note ** :
AM93LC56
Units
pF
pF
Parameter
Output capacitance
Input capacitance
Max
5
5
The parameter is characterized and isn’t 100% tested.
Functional Descriptions
Applications
The AM93LC56 is ideal for high volume applications
requiring low power and low density storage. This
device uses a low cost, space saving 8-pin package.
Typical applications include robotics, alarm devices,
electronic locks, meters and instrumentation settings
such as LAN cards, monitors and MODEM.
Endurance and Data Retention
The AM93LC56 is designed for applications
requiring up to 1M programming cycles (WRITE,
WRALL, EARSE and ERALL). It provides 40 years
of secure data retention.
Device Operation
The AM93LC56 is controlled by seven 10-bit
instructions. Instructions are clocked in (serially) on
the DI pin. Each instruction begins with a logical "1"
(the start bit). This is followed by the opcode (2 bits),
the address field (7 bits), and data, if appropriate.
The clock signal (SK) may be halted at any time and
the AM93LC56 will remain in its last state. This
allows full static flexibility and maximum power
conservation.
Read (READ)
The READ instruction is the only instruction that
outputs serial data on the DO pin. After the read
instruction and address have been decoded, data is
transferred from the selected memory register into a
8-bit or 16-bit serial shift register. (Please note that
one logical "0" bit precedes the actual 8-bit or 16-bit
output data string.) The output on DO changes
during the rising edge transitions of SK. (Shown in
Figure 3.)
Auto Increment Read Operations
Sequential read is possible, since the AM93LC56
has been designed to output a continuous stream of
memory content in response to a single read
operation instruction. To utilize this function, the
system asserts a read instruction specifying a start
location address. Once the 8-bit or 16-bit of the
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4/10
addressed word have been clocked out, the data in
consecutively higher address locations is output.
The address will wrap around continuously with CS
high until the chip select (CS) control pin is brought
low. This allows for single instruction data dumps to
be executed with a minimum of firmware overhead.
Write Enable (WEN)
Before any device programming (WRITE, WRALL,
ERASE, and ERAL) can be done, the WRITE
ENABLE (WEN) instruction must be executed first.
When Vcc is applied, this device powers up in the
WRITE DISABLE state. The device then remains in
a WRITE DISABLE state until a WEN instruction is
executed. Thereafter the device remains enabled
until a WDS instruction is executed or until Vcc is
removed. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 4.)
Write Disable (WDS)
The WRITE DISABLE (WDS) instruction disables all
programming capabilities. This protects the entire
part against accidental modification of data until a
WEN instruction is executed. (When Vcc is applied,
this part powers up in the WRITE DISABLE state.)
To protect data, a WDS instruction should be
executed upon completion of each programming
operation. (NOTE: Neither the WEN nor the WDS
instruction has any effect on the READ instruction.)
(Shown in Figure 5.)
Rev. A1 Oct 20, 2003
ATC
2048-bits Serial Electrically Erasable PROM
Functional Description (Continued)
Write (WRITE)
The WRITE instruction includes 8-bit or 16-bit of
data to be written into the specified register. After
the last data bit has been applied to DI, and before
the next rising edge of SK, CS must be brought
LOW. The falling edge of CS initiates the self-timed
programming cycle.
After a minimum wait of 250ns (5V operation) from
the falling edge of CS (tcs), DO will indicate the
READY/BUSY status of the chip if CS is brought
HIGH. This means that logical "0" implies the
programming is still in progress while logical "1"
indicates the selected register has been written, and
the part is ready for another instruction. (See Figure
6)
Note:
The combination of CS HIGH, DI HIGH and the rising edge
of the SK clock, resets the READY/BUSY flag. Therefore, it is
important if you want to access the READY/BUSY flag, not to
reset it through this combination of control signals.
AM93LC56
HIGH after a minimum wait of 250ns (tcs), the DO
pin indicates the READY/BUSY status of the chip.
(Shown in Figure 7.)
Erase (ERASE)
After the erase instruction is entered, CS must be
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