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SN74CB3Q3306
DUAL SWITCH
2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH FET BUS SWITCH
SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002
D
Low and Flat On-State Resistance (r
on
)
D
D
D
D
D
D
D
Characteristics Over Operating Range
(r
on
= 4
Ω
Typical)
0- to 5-V Rail-to-Rail Switching on Data I/O
Ports
V
CC
Operating Range From 2.3 V to 3.6 V
TTL- and LVTTL-Compatible Data I/O Ports
LVTTL-Compatible Control Inputs
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion
(C
io
= 3.5 pF Typical)
Fast Switching Speeds (f
OE
= 20 MHz Max)
D
High-Bandwidth Data Path (Up To 533 MHz)
D
Low Power Consumption
D
D
D
D
D
(I
CC
= 250
µA
Typical)
I
off
on A and B Port for Partial-Power-Down
Operation
Data and Control Inputs Provide
Undershoot Clamp Diodes
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog
Applications: PCI Hot Plug, Hot Docking,
Memory Interleaving, Bus Isolation, and
Low-Distortion Signal Gating
D OR PW PACKAGE
(TOP VIEW)
1OE
1A
1B
GND
1
2
3
4
8
7
6
5
V
CC
2OE
2B
2A
description/ordering information
Texas Instruments bus switches provide high-performance, low-power replacements for standard bus-interface
devices when signal buffering (current drive) is not required. The CB3Q family of high-bandwidth bus switches
offers low and flat on-state resistance (r
on
), 0- to 5-V rail-to-rail switching on the data input/output (I/O) ports,
and low data I/O capacitance (C
io
) to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the CB3Q family provides an optimized interface
solution ideally suited for broadband communications, networking, and data-intensive computing systems.
The SN74CB3Q3306 is a dual FET bus switch featuring independent line switches. Each switch is enabled
when the associated output-enable (OE) input is low, allowing bidirectional data flow between ports A and B.
Each switch is disabled when the associated OE input is high, producing a high-impedance state between ports
A and B. The very low r
on
of the switch allows connections to be made with minimal propagation delay.
ORDERING INFORMATION
TA
SOIC – D
TSSOP – PW
PACKAGE†
Tube
–40°C to 85°C
Tape and reel
Tape and reel
ORDERABLE
PART NUMBER
SN74CB3Q3306D
SN74CB3Q3306DR
SN74CB3Q3306PWR
BU306
BU306
TOP-SIDE
MARKING
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002
SN74CB3Q3306
DUAL SWITCH
2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH FET BUS SWITCH
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry prevents damaging
current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
(each bus switch)
INPUT
OE
L
H
FUNCTION
A port = B port
Disconnect
logic diagram (positive logic)
1A
2
3
1B
1
1OE
5
2A
7
2OE
6
2B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I
IK
(V
I/O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN
VCC
VIH
VIL
Supply voltage
High-level
High le el control inp t voltage
input oltage
Low-level
Lo le el control inp t voltage
input oltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
2.3
1.7
2
0.7
0.8
V
V
MAX
3.6
UNIT
V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74CB3Q3306
DUAL SWITCH
2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH FET BUS SWITCH
SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
IIN
IOZ‡
Ioff
ICC
∆I
CC§
ICCD¶
Cin
Cio(ON)
Control inputs
Control inputs
Control inputs
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 0,
VCC = 3.6 V,
VCC = 3.6 V,
TEST CONDITIONS
II = –18 mA
VIN = 5.5 V or GND
VI/O = VCC or GND
VI/O = 0 to 5.5 V
II/O = 0,
One input at 3 V,
VIN = VCC or GND
Other inputs at VCC or GND
250
MIN
TYP†
MAX
–1.8
±1
±1
±1
700
25
0.03
2.5
Switch off, OE = VCC
Switch on, OE = GND
IO = 30 mA
IO = –15 mA
IO = 30 mA
IO = –15 mA
3.5
8
4
5
4
0.1
3.5
5
10.5
8
9
6
Ω
UNIT
V
µA
µA
µA
µA
µA
mA/
MHz
pF
pF
pF
VCC = 3.6 V, A and B pins open,
Per OE control input switching at 50% duty cycle
VIN = 5.5 V, 3.3 V, or 0,
VI/O = 5.5 V, 3.3 V, or 0,
VI/O = 5.5 V, 3.3 V, or 0,
VCC = 2.3 V,
TYP at VCC = 2.5 V
VCC = 3 V
VCC = 3.3 V
VCC = 3.3 V,
VCC = 3.3 V,
VI = 0,
VI = 1.7 V,
VI = 0,
Cio(OFF)
ron#
VI = 2.4 V,
5
8
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
† All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
¶ This parameter specifies the dynamic power-supply current associated with the operating frequency of a single OE control input. The total ICC
can be calculated with the following formula: Total ICC = ICC + (ICCD
×
1OE frequency) + (ICCD
×
2OE frequency).
# Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
PARAMETER
fOE||
tpd
k
ten
tdis
FROM
(INPUT)
OE
A or B
OE
OE
TO
(OUTPUT)
A or B
B or A
A or B
A or B
1.5
1
VCC = 2.5 V
±
0.2 V
MIN
MAX
10
0.2
6.5
6
1.5
1
VCC = 3.3 V
±
0.3 V
MIN
MAX
20
0.2
5.5
5
MHz
ns
ns
ns
UNIT
|| Maximum toggle frequency for OE control input (VO
>
VCC, VI = 5 V, RL
≥
1 MΩ, CL = 0)
k
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCDS113A – DECEMBER 2002 – REVISED DECEMBER 2002
SN74CB3Q3306
DUAL SWITCH
2.5 V/3.3 V LOW VOLTAGE, HIGH BANDWIDTH FET BUS SWITCH
TYPICAL r
on
vs
V
I
16
r
on
– On-State Resistance –
Ω
14
12
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
VI – V
3.0
3.5
4.0
4.5
5.0
VCC = 3.3 V
TA = 25°C
IO = –15 mA
Figure 1. Typical r
on
vs V
I
, V
CC
= 3.3 V and I
O
= –15 mA
TYPICAL I
CC
vs
OE SWITCHING FREQUENCY
12
10
8
6
4
All OE Switching
2
0
0
2
4
6
8
10
12
14
16
18
20
OE Switching Frequency – MHz
One OE Switching
VCC = 3.3 V
TA = 25°C
ICC – mA
Figure 2. Typical I
CC
vs OE Switching Frequency, V
CC
= 3.3 V
4
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