IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
FAST CMOS
BUFFER/CLOCK DRIVER
IDT74FCT810BT/CT
FEATURES:
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
Guaranteed low skew < 600ps (max.)
Very low duty cycle distortion < 700ps (max.)
Low CMOS levels
TTL compatible inputs and outputs
TTL level output voltage swings
High drive: -32mA I
OH
, +48mA I
OL
Two independent output banks with 3-state control:
– One 1:5 inverting bank
– One 1:5 non-inverting bank
• Available in QSOP, SSOP, and SOIC packages
DESCRIPTION:
The 74FCT810T is a dual bank inverting/ non-inverting clock driver
built using advanced dual metal CMOS technology. It consists of two banks
of drivers, one inverting and one non-inverting. Each bank drives five output
buffers from a standard TTL-compatible input. The FCT810T has low output
skew, pulse skew and package skew. Inputs are designed with hysteresis
circuitry for improved noise immunity. The outputs are designed with TTL
output levels and controlled edge rates to reduce signal noise. The part has
multiple grounds, minimizing the effects of ground inductance.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
OB
1
OB
2
OB
3
GND
OB
4
OB
5
GND
OE
B
IN
B
OE
A
5
IN
A
OA
1
-O A
5
OA
1
OA
2
OA
3
GND
OA
4
OE
B
OA
5
5
IN
B
O B
1
-O B
5
GND
OE
A
IN
A
QSOP/ SOIC/ SSOP
TOP VIEW
COMMERCIAL TEMPERATURE RANGE
1
c
2001
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MAY 2010
DSC-4646/3
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–65 to +150
–60 to +120
Unit
V
°C
mA
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4.5
5.5
Max.
6
8
Unit
pF
pF
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
OE
A
,
OE
B
IN
A
, IN
B
OAx,
OBx
Clock Inputs
Clock Outputs
Description
3-State Output-Enable Inputs (Active LOW)
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= 0°C to +70°C, V
CC
= 5V ± 5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
I
OS
V
OH
V
OL
I
OFF
V
H
I
CCL
I
CCH
I
CCZ
Parameter
Input HIGH Level (Input pins)
Input LOW Level
Input HIGH Current (Input pins)
Input LOW Current (Input pins)
High Impedance Output Current
(3-State Output pins)
Input HIGH Current
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Output LOW Voltage
Input/Output Power Off Leakage
Input Hysteresis for all inputs
Quiescent Power Supply Current
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 0V, V
IN
or V
O
≤
4.5V
—
V
CC
= Max., V
IN
= GND or V
CC
—
—
—
—
150
5
±1
—
500
µA
mV
µA
I
OH
= –15mA
I
OH
= –32mA
(4)
I
OL
= 48mA
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max.
V
I
= 2.7V
V
I
= 0.5V
V
O
= 2.7V
V
O
= 0.5V
Min.
2
—
—
—
—
—
—
—
–60
2.4
2
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
–120
3.3
3
0.3
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
–225
—
—
0.55
V
µA
V
mA
V
Unit
V
V
µA
µA
µA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 5V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition should not exceed one second.
2
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
A
=
OE
B
= GND
50% Duty Cycle
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
f
O
= 25MHz
50% Duty Cycle
OE
A
= GND,
OE
B
= V
CC
V
CC
= Max.
Outputs Open
f
O
= 50MHz
50% Duty Cycle
OE
A
=
OE
B
= GND
NOTES:
1.
2.
3.
4.
5.
For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
Typical values are at V
CC
= 5V, +25°C ambient.
Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
Values for these conditions are examples of the I
C
formula. These limits are guaranteed but not tested.
6.
I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
O
N
O
)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input (V
I
N
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
O
= Output Frequency
N
O
= Number of Outputs at f
O
All currents are in milliamps and all frequencies are in megahertz.
Test Conditions
(1)
Min.
—
Typ.
(2)
0.5
60
Max.
2
100
Unit
mA
µA/MHz
V
IN
= V
CC
V
IN
= GND
—
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
7.5
13
mA
—
—
7.8
30
14
50.5
(5)
—
30.5
52.5
(5)
3
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(3,4)
FCT810BT
Symbol
t
PLH
t
PHL
t
R
t
F
t
SK1(O)
t
SK2(O)
t
SK(P)
t
SK(T)
Parameter
Propagation Delay
IN
A
to OAx, IN
A
to
OBx
Output Rise Time
Output Fall Time
Output skew (same bank): skew between outputs of
same bank and same package (same transition)
Output skew (all banks): skew between outputs of
all banks of same package (inputs tied together)
Pulse skew: skew between opposite transitions
of same output (|t
PHL -–
t
PLH
|)
Package skew: skew between outputs of different
packages at same power supply voltage,
temperature, package type and speed grade
t
PZL
t
PZH
t
PLZ
t
PHZ
Output Enable Time
OE
A
to OAx,
OE
B
to
OBx
Output Disable Time
OE
A
to OAx,
OE
B
to
OBx
1.5
1.5
6
6
1.5
1.5
5
5
ns
ns
—
1.2
—
1
ns
Conditions
(1)
C
L
= 50pF
R
L
= 500Ω
—
—
—
—
—
1.5
1.5
0.5
0.7
0.7
—
—
—
—
—
1.5
1.5
0.3
0.6
0.7
ns
ns
ns
ns
ns
Min
.
(2)
1.5
Max
.
4.5
FCT810CT
Min
.
(2)
1.5
Max
.
4.3
Unit
ns
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. t
PLH
, t
PHL
, t
SK
(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to V
CC
, operating temperature and process parameters. These propagation delay limits do not imply skew.
4
IDT74FCT810BT/CT
FAST CMOS BUFFER/CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
7.0V
SWITCH POSITION
Test
Switch
Closed
GND
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
500
V
IN
Pulse
Generator
R
T
V
OUT
D.U.T.
50pF
500
C
L
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Test Circuit for All Outputs
3V
INPUT
1.5V
INPUT
t
PLH
t
PH L
V
OH
2.0V
OUTPUT
t
R
t
F
0.8V
1.5V
V
OL
OUTPUT 2
t
PLH2
t
PH L2
0V
OUTPUT 1
t
SK(o)
t
SK(o)
t
PLH1
t
PHL1
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
SK(o)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
Package Delay
3V
1.5V
0V
V
OH
OUTPUT 1
t
SK(o)
OUTPUT 2
t
PLH2
t
SK(o)
V
OH
1.5V
V
OL
t
PH L2
t
SK(o)
= |t
PLH2 -
t
PLH1
|
or
|t
PHL2 -
t
PHL1
|
OUTPUT
1.5V
V
OL
INPUT
Output Skew (Same Bank) - t
SK1(O)
INPUT
3V
1.5V
0V
t
PLH
t
PH L
V
OH
1.5V
V
OL
t
SK(p)
= |t
PHL -
t
PLH
|
t
PLH1
t
PH L1
Pulse Skew - t
SK(P)
Output Skew (All Banks) - t
SK2(O)
3V
INPUT
1.5V
0V
V
OH
1.5V
PACKAGE 1 OUTPUT
t
SK2(o)
t
SK2(o)
V
OL
V
OH
1.5V
V
OL
CONTROL
INPUT
t
OUTPUT
NORMA LLY
LOW
PZL
ENABLE
DISABLE
3V
1.5V
0V
t
3.5V
1.5V
0.3V
t
1.5V
0V
0V
PHZ
PLZ
t
PD 1a
t
PD 1b
SW ITCH
CLOSE D
t
PZH
3.5V
V
OL
V
OH
PACKAGE 2 OUTPUT
t
PD2a
t
PD2b
or
t
SK(t)
= |t
PD2a -
t
PD1a
|
|t
PD 2b -
t
PD1b
|
OUTPUT
NORMA LLY
HIGH
SW ITCH
OPEN
0.3V
Package Skew - t
SK(T)
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
Enable and Disable Times
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
5
国产芯片交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
