FemtoClock
®
Crystal/LVCMOS-to-
LVDS/LVCMOS Frequency Synthesizer
ICS8440258-46
DATA SHEET
General Description
The ICS8440258-46 is an eight output synthesizer optimized to
generate Ethernet clocks. The device will generate 125MHz and
25MHz clocks from a 25MHz crystal with a very good jitter
performance. The ICS8440258-46 uses IDT’s 3
RD
generation low
phase noise VCO technology. The ICS8440258-46 is packaged in a
small, 5mm x 5mm VFQFN package.
Features
•
•
•
•
•
•
nPLL_SEL
V
DDA
Four differential LVDS outputs at 125MHz
Two LVCMOS/LVTTL single-ended outputs at 125MHz
Two LVCMOS/LVTTL single-ended outputs at 25MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.5ps (typical)
Full 2.5V supply mode
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Pin Assignment
nXTAL_SEL
XTAL_OUT
REF_CLK
XTAL_IN
V
DD
MR
32 31 30
Q0
nQ0
GND
Q1
nQ1
V
DD
Q2
nQ2
1
2
3
4
5
6
7
8
9
29 28
27 26 25
24
23
22
21
20
19
18
17
nc
nc
nc
GND
Q7
V
DDO2
Q6
GND
10 11 12 13 14 15 16
ICS8440258-46
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
3.15mm x 3.15mm ePad size
K Package
Top View
V
DDO1
GND
GND
nQ3
V
DD
Q3
Q4
Q5
Block Diagram
MR
Pulldown
Q0
Pulldown
nPLL_SEL
nQ0
Q1
nQ1
25MHz
XTAL_IN
Q2
OSC
XTAL_OUT
REF_CLK
Pulldown
0
Phase
Detector
1
1
÷5
VCO
0
nQ2
Q3
nQ3
Q4
nXTAL_SEL
Pulldown
÷25
Q5
Q6
Q7
ICS8440258CK-46 REVISION A OCTOBER 18, 2013
1
©2013 Integrated Device Technology, Inc.
ICS8440258-46 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 2
3, 12,
16, 17, 21
4, 5
6, 11, 27
7, 8
9, 10
13, 15, 18, 20
14
19
22, 23, 24
25
Name
Q0, nQ0
GND
Q1, nQ1
V
DD
Q2, nQ2
Q3, nQ3
Q4, Q5, Q6, Q7
V
DDO1
V
DDO2
nc
V
DDA
Output
Power
Output
Power
Output
Output
Output
Power
Power
Unused
Power
Type
Description
Differential clock outputs. LVDS interface levels.
Power supply ground.
Differential clock outputs. LVDS interface levels.
Core supply pins.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Output supply pin for Q4 and Q5 LVCMOS outputs.
Output supply pin for Q6 and Q7 LVCMOS outputs.
No connect.
Analog supply pin.
PLL Bypass. When LOW, Q[0:3], nQ[0:3], Q4, Q5 is driven from the
VCO output. When HIGH, the PLL is bypassed and Q[0:3], nQ[0:3], Q4,
Q5 output frequency = reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between the crystal or REF_CLK inputs as the PLL reference
source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_OUT is the output, XTAL_IN is the
input.
26
nPLL_SEL
Input
Pulldown
28
29
30
31,
32
MR
REF_CLK
nXTAL_SEL
XTAL_OUT,
XTAL_IN
Input
Input
Input
Pulldown
Pulldown
Pulldown
Input
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input
Capacitance
Power
Dissipation
Capacitance
(per output)
REF_CLK,
nXTAL_SEL,
MR, nPLL_SEL
Q[4:5]
Q[6:7]
V
DDO1,
V
DDO2
= 2.625V
V
DDO1,
V
DDO2
= 2.625V
Test Conditions
Minimum
Typical
4
12
7
51
V
DDO1,
V
DDO2
= 2.5V
V
DDO1,
V
DDO2
= 2.5V
11
22
Maximum
Units
pF
pF
pF
k
C
PD
R
PULLDOWN
R
OUT
Input Pulldown Resistor
Output
Impedance
Q[4:5]
Q[6:7]
ICS8440258CK-46 REVISION A OCTOBER 18, 2013
2
©2013 Integrated Device Technology, Inc.
ICS8440258-46 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDOx
+ 0.5V
10mA
15mA
0C to +70C
33.1C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO1
= V
DDO2
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
V
DDO1,
V
DDO2
I
DD
I
DDA
I
DDO1
+ I
DDO2
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Outputs Unterminated
Outputs Unterminated
Outputs Unterminated
Test Conditions
Minimum
2.375
V
DD
– 0.15
2.375
Typical
2.5
2.5
2.5
170
13
Maximum
2.625
V
DD
2.625
187
15
6
Units
V
V
V
mA
mA
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDO1
= V
DDO2
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
Input Low
Current
Output High
Voltage
Output Low
Voltage
nXTAL_SEL,
MR, REF_CLK,
nPLL_SEL
nXTAL_SEL,
MR, REF_CLK,
nPLL_SEL
Q[4:7]
Q[4:7]
V
DD
= V
IN
= 2.625V
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
150
Units
V
V
µA
I
IL
V
DD
= 2.625V, V
IN
= 0V
V
DDO1,
V
DDO2 =
2.5V
±5%;
-5
µA
V
OH
V
OL
I
OH
= -12mA
V
DDO1,
V
DDO2 =
2.5V
±5%;
1.8
0.5
V
V
I
OL
= 12mA
ICS8440258CK-46 REVISION A OCTOBER 18, 2013
3
©2013 Integrated Device Technology, Inc.
ICS8440258-46 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
Table 3C. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
0.85
1.2
Test Conditions
Minimum
300
Typical
400
Maximum
485
50
1.55
50
Units
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance
Shunt Capacitance
Load Capacitance
12
Test Conditions
Minimum
Typical
Fundamental
25
50
7
18
MHz
Maximum
Units
pF
pF
ICS8440258CK-46 REVISION A OCTOBER 18, 2013
4
©2013 Integrated Device Technology, Inc.
ICS8440258-46 Data Sheet
FEMTOCLOCK
®
CRYSTAL/LVCMOS-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= V
DDO1
= V
DDO2
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
Parameter
Q[0:3], nQ[0:3]
f
OUT
Output
Frequency
Q4, Q5
Q6, Q7
Q[0:3], nQ[0:3];
NOTE 1A
Q[4:5]; NOTE 1B
Q[6:7]; NOTE 1B
125MHz, Integration Range:
1.875MHz - 20MHz
Q[0:3], nQ[0:3]
tjit(Ø)
RMS Phase
Noise Jitter
(Random);
NOTE 3
Q4, Q5
125MHz, Integration Range:
12kHz - 20MHz
Output
Rise/Fall
Time
Output
Duty Cycle
Q[0:3], nQ[0:3]
Q[4:5]
Q[6:7]
Q[0:3], nQ[0:3]
Q[4:5]
20% to 80%
20% to 80%
20% to 80%
330
250
0.78
45
45
1.188
600
450
2.7
55
55
ps
ps
ps
ns
%
%
125MHz, Integration Range:
12kHz - 20MHz
125MHz, Integration Range:
1.875MHz - 20MHz
1.149
0.5
ps
ps
0.5
nPLL_SEL = 0
nPLL_SEL = 0
Test Conditions
Minimum
Typical
125
125
25
40
80
80
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
tsk(o)
Output Skew;
NOTE 2
t
R
/ t
F
odc
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Device characterized with a 25MHz, 12pF quartz crystal.
NOTE 1A: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
point.
NOTE 1B: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDOX
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Refer to Phase Noise Plots.
ICS8440258CK-46 REVISION A OCTOBER 18, 2013
5
©2013 Integrated Device Technology, Inc.
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