3.3V, 2GHz ANY-DIFFERENTIAL
Precision Edge™
SY89833L
INPUT-TO-LVDS 1:4 FANOUT BUFFER/
FINAL
TRANSLATOR W/ INTERNAL TERMINATION
FEATURES
I
Accepts any differential input signal and provides
four LVDS output copies
I
Guaranteed AC performance over temperature
and voltage:
• > 2.0GHz f
MAX
• < 20ps within-device skew
• < 190ps rise/fall times
I
Low jitter design
• < 1ps(rms) cycle-to-cycle jitter
• < 10ps(pk-pk) total jitter
I
3.3V power supply operation
I
TTL/CMOS input for enable
I
Unique input termination and V
T
pin accepts DC-
coupled and AC-coupled inputs (CML, PECL, LVDS,
and HSTL)
I
High-speed LVDS outputs
I
Wide operating temperature range: –40
°
C to +85
°
C
I
Available in 16-pin (3mm
×
3mm) MLF™ package
Precision Edge™
DESCRIPTION
The SY89833L is a 3.3V, high-speed 2GHz differential
Low Voltage Differential Swing (LVDS) 1:4 fanout buffer
optimized for ultra-low skew applications. Within device skew
is guaranteed to be less than 20ps over supply voltage and
temperature.
The differential input buffer has a unique internal
termination design that allows access to the termination
network through a V
T
pin. This feature allows the device to
easily interface to different logic standards. A V
REF_AC
reference is included for AC-coupled applications.
The SY89833L is part of Micrel’s high-speed clock
synchronization family. For 2.5V applications, the SY89832U
provides similar functionality while operating from a 2.5V
±5%
supply. For applications that require a different I/O
combination, consult the Micrel website at
www.micrel.com,
and choose from a comprehensive product line of high-
speed, low-skew fanout buffers, translators and clock
generators.
APPLICATIONS
I
I
I
I
Processor clock distribution
SONET clock distribution
Fibre Channel clock distribution
Gigabit Ethernet clock distribution
FUNCTIONAL BLOCK DIAGRAM
Q0
/Q0
TYPICAL PERFORMANCE
622MHz Output
Q1
IN
V
T
/IN
50Ω
50Ω
/Q1
Q2
/Q2
EN
V
REF—AC
D
Q
Q3
/Q3
–15mV Offset
(50mV/div.)
TIME (321.9ps/div.)
Precision Edge is a trademark of Micrel, Inc.
MicroLeadFrame
and MLF are trademarks of Amkor Technology, Inc.
Rev.: D
Amendment: /0
1
Issue Date: February 2003
Micrel
Precision Edge™
SY89833L
PACKAGE/ORDERING INFORMATION
/Q0
Q0
VCC
GND
Ordering Information
Part Number
Package
Type
MLF-16
MLF-16
Operating
Range
Industrial
Industrial
Package
Marking
833L
833L
16 15 14 13
Q1
/Q1
Q2
/Q2
1
2
3
4
5 6 7 8
Q3
/Q3
VCC
EN
12
11
10
9
IN
VT
VREF—AC
/IN
SY89833LMI
SY89833LMITR*
*Tape and Reel
16-Pin MLF™
PIN DESCRIPTION
Pin Number
15, 16,
1, 2, 3, 4, 5, 6
8
Pin Name
(Q0, /Q0)
to
(Q3, /Q3)
EN
Pin Function
LVDS Differential (Outputs): Normally terminated with 100Ω across the pair (Q, /Q). See
“LVDS Outputs”
section, Figure 2a. Unused outputs should be terminated with a 100Ω
resistor across each pair.
TTL/CMOS Compatible Synchronous Enable: When EN goes LOW, Q outputs will go
LOW and /Q outputs will go HIGH on the next LOW transition at IN inputs. Input threshold
is V
CC
/2V. A 25kΩ pull-up resistor is included. The default state is HIGH when left floating.
The internal latch is clocked on the falling edge of the input signal (IN, /IN).
Differential Clock (Inputs): Internal 50Ω termination resistors to the V
T
pin.
See
“Input Interface Applications”
section.
Reference Voltages: Equals to V
CC
–1.4V, and is used for AC-coupled applications.
The maximum sink/source current is 0.5mA. See
“Input Interface Applications.”
When using V
REF–AC
, bypass with a 0.01µF capacitor to V
CC
.
Termination Center-Tap. For CML or LVDS inputs, leave this pin floating. See Figures
3a to 3f. See
“LVDS Outputs”
Figures 2a and 2b for LVDS differential and common
mode measurements.
Ground. Exposed pad internally connected to GND and must be connected to a ground
plane for proper thermal operation.
Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors.
9, 12
10
/IN, IN
VREF–AC
11
VT
13,
Exposed Pad
7, 14
GND
VCC
TRUTH TABLE
IN
0
1
X
Note 1.
/IN
1
0
X
EN
1
1
0
Q
0
1
0
(1)
/Q
1
0
1
(1)
On next negative transition of the input signal (IN).
2
Micrel
Precision Edge™
SY89833L
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
) .................................. –0.5V to +4.0V
Input Voltage (V
IN
) ............................... –0.5V to V
CC
+0.3V
Output Current (I
OUT
) ...............................................
±10mA
Input Current (IN, /IN) ...............................................
±50mA
V
T
Current (I
VT
) ......................................................
±100mA
Input Sink/Source Current (V
REF–AC
),
Note 3 ............
±2mA
Lead Temperature (Soldering, 10 sec.) .................... 220°C
Storage Temperature (T
S
) ....................... –65°C to +150°C
Note 1.
Operating Ratings
(Note 2)
Supply Voltage Range ............................ +2.97V to +3.63V
Ambient Temperature (T
A
) ......................... –40°C to +85°C
Package Thermal Resistance
MLF™
(θ
JA
)
Still-Air ............................................................. 60°C/W
500lfpm ............................................................ 54°C/W
MLF™
(ψ
JB
),
Note 4
........................................... 32°C/W
Note 2.
Note 3.
Note 4.
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is
not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to ABSOLUTE MAXIMUM RATlNG
conditions for extended periods may affect device reliability.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
Due to the limited drive capability use for input of the same package only.
Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB.
DC ELECTRICAL CHARACTERISTICS
(Note 1, 2)
T
A
= –40°C to +85°C
Symbol
V
CC
I
CC
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
|I
IN
|
V
REF–AC
Note 1.
Note 2.
Note 3.
Parameter
Power Supply Voltage Range
Power Supply Current
Differential Input Resistance
(IN, /IN)
Input HIGH Voltage
(IN, /IN)
Input LOW Voltage
(IN, /IN)
Input Voltage Swing
Differential Input Voltage
Input Current
(IN, /IN)
Reference Voltage
Condition
Min
2.97
Typ
3.3
75
Max
3.63
100
120
V
CC
+0.3
V
CC
+0.2
3.6
Units
V
mA
Ω
V
V
V
V
No Load
80
Note 3
Note 3
Note 3,
see Figure 2c
V
IN
(max), V
T
= floating.
Note 3,
see Figure 2d
Note 3
Note 3
0.1
–0.3
0.1
0.2
100
45
V
CC
–1.525 V
CC
–1.425 V
CC
–1.325
mA
V
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
Due to the internal termination (see
“Differential Input”)
the input current depends on the applied voltages at IN, /IN and V
T
inputs. Do not apply
a combination of voltages that causes the input current to exceed the maximum limit.
3
Micrel
Precision Edge™
SY89833L
LVDS OUTPUTS DC ELECTRICAL CHARACTERISTICS
(Note 1, 2)
V
CC
= 3.3V
±10%,
T
A
= –40°C to +85°C
Symbol
V
OH
V
OL
V
OCM
∆V
OCM
V
OUT
V
DIFF_OUT
Note 1.
Note 2.
Note 3.
Parameter
Output HIGH Voltage
Output LOW Voltage
Output Common Mode Voltage
Change in Common Mode Voltage
Single-Ended Output
Differential Output
Condition
Note 3
Note 3
Min
Typ
Max
1.475
Units
V
V
0.925
1.125
–50
1.275
50
350
700
450
900
V
mV
mV
mV
see Figures 2c-2d
see Figures 2c-2d
250
500
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
Measured as per Figure 2a, 100Ω across Q and /Q outputs.
LVTTL/CMOS INPUTS DC ELECTRICAL CHARACTERISTICS
(Note 1, 2)
V
CC
= 3.3V
±10%,
T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
Note 1.
Note 2.
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Condition
Min
2.0
0
–125
Typ
Max
V
CC
0.8
20
–300
Units
V
V
µA
µA
The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Specification for packaged product only.
4
Micrel
Precision Edge™
SY89833L
AC ELECTRICAL CHARACTERISTICS
(Note 1, 2)
V
CC
= 3.3V
±10%,
T
A
= –40°C to +85°C
Symbol
f
MAX
t
PLH
t
PHL
t
SKEW
t
S
t
H
t
JITTER
t
r
, t
f
Note 1.
Note 2.
Note 3.
Note 4.
Note 5.
Note 6.
Note 7.
Parameter
Maximum Frequency
Differential Propagation
(Delay) (IN-to-Q)
Within-Device Skew (Differential)
Part-to-Part Skew (Differential)
Set-Up Time (EN to IN, /IN)
Hold Time (EN to IN, /IN)
Cycle-to-Cycle Jitter (rms)
Total Jitter
Output Rise/Fall Times
(20% to 80%)
Condition
≥200mVpp
Output Swing
Input Swing: <400mV
Input Swing:
≥400V
Note 3
Min
2.0
400
330
Typ
Max
Units
GHz
500
440
5
600
530
20
200
ps
ps
ps
ps
ps
ps
Note 4 and Note 5
Note 4 and Note 5
Note 6
Note 7
300
500
1
10
60
110
190
ps(rms)
ps(pk-pk)
ps
Measured with 400mV input signal, 50% duty cycle, all outputs are loaded with 100Ω between Q and /Q. Output swing is
≥
200mV.
Specification for packaged product only.
Skew is measured between outputs under identical transitions.
Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applica-
tions set-up and hold times do not apply.
See
“Timing Diagram.”
Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs.
T
JITTER_CC
= T
n
–T
n+1
where T is the time between rising edges of the output signal.
Total jitter definition: with an ideal clock input frequency of
≤
f
MAX
(device), no more than one output edge in 10
12
output edges will deviate by more
than the specified peak-to-peak jitter value.
TIMING DIAGRAM
EN
V
CC
/2
t
S
/IN
IN
V
IN
t
PLH
, t
PHL
/Q
Q
V
OUT
Swing
t
PLH
,t
PHL
t
H
V
CC
/2
5
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