CMOS PARALLEL-SERIAL FIFO
2,048 x 9 and 4,096 x 9
Integrated Device Technology, Inc.
IDT72103
IDT72104
FEATURES:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial input/output frequency
• Serial-to-parallel, parallel-to-serial, serial-to-serial, and
parallel-to-parallel operations
• Expandable in both depth and width with no external
components
• Flexishift™ — Sets programmable serial word width
from 4 bits to any width with no external components
• Multiple flags: Full, Almost-Full (Full-1/8),Full-Minus-
One, Empty, Almost-Empty (Empty + 1/8), Empty-Plus-
One, and Half-Full
• Asynchronous and simultaneous read or write operations
• Dual-Port, zero fall-through time architecture
• Retransmit capability in single-device mode
• Packaged in 44-pin PLCC
• Industrial temperature range (–40
o
C to +85
o
C)
APPLICATIONS:
•
•
•
•
•
•
•
•
•
High-speed data acquisition systems
Local area network (LAN) buffer
High-speed modem data buffer
Remote telemetry data buffer
FAX raster video data buffer
Laser printer engine data buffer
High-speed parallel bus-to-bus communications
Magnetic media controllers
Serial link buffer
DESCRIPTION:
The IDT72103/72104 are high-speed Parallel-Serial FlFOs
to be used with high-performance systems for functions such
as serial communications, laser printer engine control and
local area networks.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
INPUT
SI
SIX
SICP
/PI
/PO
DATA INPUTS (D
0
-D
8
)
SERIAL
INPUT
CIRCUITRY
FLAG
LOGIC
SERIAL/
PARALLEL
CONTROL
RAM ARRAY
2048 x 9
4096 x 9
WRITE
POINTER
READ
POINTER
/
DEPTH
EXPANSION
LOGIC
RESET
LOGIC
SERIAL
OUTPUT
CIRCUITRY
DATA OUTPUTS (Q
0
-Q
8
)
The IDT logo is a registered trademark of Integrated Device Technology,Inc.
SERIAL
OUTPUT
SO
SOX
SOCP
2753 drw 01
INDUSTRIAL TEMPERATURE RANGE
©1999 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
DECEMBER 1999
DSC-2753/-
1
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
DESCRIPTION (Continued)
A serial input, a serial output and two 9-bit parallel ports
make four modes of data transfer possible: serial-to-parallel,
parallel-to-serial, serial-to-serial, and parallel-to-parallel. These
devices are expandable in both depth and width for all of these
operational configurations.
These FIFOs may be configured to handle serial word
widths of four or greater using IDT’s unique Flexishift feature.
Flexishift allows serial width and depth expansion without
external components. For example, you may configure a 4K
x 24 FIFO using three IDT72104s in a serial width expansion
configuration.
Seven flags are provided to signal memory status of the
FIFO. The flags are
FF
(Full),
AF
(7/8 full),
FF–1
(Full-minus-
one),
EF
(Empty),
AE
(1/8 full),
EF+1
(Empty-plus-one), and
HF
(Half-full).
Read (
R
) and Write (
W
) control pins are provided for
asynchronous and simultaneous operations. An Output En-
able (
OE
) control pin is available on the parallel output port for
high-impedance control. The depth expansion control pins
XO
and
Xl
are provided to allow cascading for deeper FlFOs.
The IDT72103/72104 are manufactured using IDT’s CMOS
technology.
PIN CONFIGURATIONS
GND
D
1
D
2
D
3
D
4
6
5
4
3
2
1
INDEX
D
0
/PO
SOX
SOCP
SO
V
CC
D
5
D
6
D
7
D
8
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
7
8
9
10
11
12
13
14
15
GND
/
SI
SICP
SIX
Q
0
GND
16
17
29
18 19 20 21 22 23 24 25 26 27 28
/
2753 drw 03
Q
1
Q
2
Q
3
Q
4
GND
PLCC (J44-1, order code: J)
TOP VIEW
Q
5
Q
6
Q
7
Q
8
GND
2
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
Name
D
0
-D
8
Data Inputs
Serial Input Word
Width Select
RS
Reset
I/O
Description
I/O In a parallel input configuration – data inputs for 9-bit wide data.
In a serial input configuration – one of the nine output pins is used to select the serial input
word width.
I When
RS
is set low, internal READ and WRITE pointers are set to the first location of the RAM
array.
EF
,
EF+1
,
AEF
are all LOW after a reset, while
FF
,
FF-1
,
HF
are HIGH after a reset.
W
Write
I A parallel word write cycle is initiated on the falling edge of
W
if the
FF
is high. When the FIFO
is full,
FF
will go low inhibiting further write operations to prevent data overflow. In a serial
input configuration, data bits are clocked into the input shift register and the write pointer does
not advance until a full parallel word is assembled. One of the pins, D
i
, is connected to
W
and
advances the write pointer every i-th serial input clock.
R
Read
I A read cycle is initiated on the falling edge of
R
if the
EF
is HIGH. After all the data from the
FIFO has been read
EF
will go LOW inhibiting further read operations. In a serial output
configuration, a data word is read from memory into the output shift register. One of the pins,
Q
j
, is connected to
R
and advances the read pointer every j-th serial output clock.
FL
/
RT
First Load/
I This is a dual-purpose pin. In multiple-device mode,
FL
/
RT
is grounded to indicate the first
Retransmit
device loaded. In single-device mode,
FL
/
RT
acts as the retransmit input. Single-device mode
is initiated by grounding the
XI
pin.
Xl
Expansion In
I In single-device mode,
XI
is grounded. In depth expansion or daisy chain mode,
XI
is con-
nected to the
XO
pin of the previous device.
OE
Output Enable
I When
OE
is LOW, both parallel and serial outputs are enabled. When
OE
is HIGH, the parallel
output buffers are placed in a high-impedance state.
Q
0
-Q
8
Data Outputs/Serial
O In a parallel output configuration - data outputs for 9-bit wide data. In a serial output
Output Word Width Select
configuration - one of nine output pins used to select the serial output word width.
FF
Full Flag
O
FF
is asserted LOW when the FIFO is full and further write operations are inhibited. When
the
FF
is HIGH, the FIFO is not full and data can be written into the FIFO.
FF-1
Full-1 Flag
O
FF-1
goes LOW when the FIFO memory array is one word away from being full. It will remain
LOW when every memory location is filled.
XO
/
HF
Expansion Out/
O
HF
is LOW when the FIFO is more than half-full in the single device or width expansion modes.
Half-Full Flag
The
HF
will remain LOW until the difference between the write and read pointers is less than
or equal to one-half of the FIFO memory.
In depth expansion mode, a pulse is written from
XO
to
XI
of the next device when the last
location in the FIFO is filled. Another pulse is sent from
XO
to
Xl
of the next device when the
last FIFO location is read.
AEF
Almost-Empty/
O When
AEF
is LOW, the FIFO is empty to 1/8 full or 7/8 full to completely full. If
AEF
is HIGH,
Almost-Full Flag
then the FIFO is greater than 1/8 full, but less than 7/8 full.
EF+1
Empty+1 Flag
O
EF+ 1
is LOW when there is zero or one word in the FIFO memory array.
EF
Empty Flag
O
EF
goes LOW when the FIFO is empty and further read operations are inhibited.
FF
is HIGH
when the FIFO is not empty and data reads are permitted.
Sl
Serial Input Expansion
I Data input for serial data.
SO
Serial Output Expansion
O Data output for serial data.
SICP Serial Input Clock
I This pin is the serial input clock. On the rising edge of the SICP signal, new serial data bits
are read into the serial input shift register.
SOCP Serial Output
I This pin is the serial output clock. On the rising edge of the SOCP signal, new serial data bits
Clock
are read from the serial output shift register.
SIX
Serial Input
I SIX controls the serial input expansion for word widths greater than 9 bits. In a serial input
Expansion
configuration, the SIX pin of the least significant device is tied HIGH. The SIX pin of all other
devices is connected to the D
8
pin of the previous device. In parallel input configurations or
serial input configurations of 9 bits or less, SIX is tied HIGH.
SOX
Serial Output
I SOX controls the serial output expansion for word widths greater than 9 bits. In a serial output
Expansion
configuration, the SOX pin of the least significant device is tied HIGH. The SOX pin of all other
devices is connected to the Q
8
pin of the previous device. In parallel output configurations or
serial output configurations of 9 bits or less, SOX is tied HIGH.
SI
/PI Serial/Parallel Input
I When this pin is HIGH, the FIFO is in a parallel input configuration and accepts input data through
D
0
-D
8
. When
SI
/PI is LOW, the FIFO is in a serial input configuration and data is input through Sl.
SO
/PO Serial/Parallel Output
I When this pin is HIGH, the FIFO is in a parallel output configuration and sends output data through
Q
0
-Q
8
. When
SO
/PO is LOW the FIFO is in a serial output configuration and data is input through SO.
GND Ground
Five ground pins for the PLCC.
V
CC
Power
One + 5V power pin.
2753 tbl 04
3
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9, 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
STG
I
OUT
Rating
Terminal Voltage
with Respect to GND
Storage Temperature
DC Output Current
Commercial
–0.5 to +7.0
–55 to +125
–50 to +50
Unit
V
°C
mA
RECOMMENDED DC OPERATING CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
(1)
T
A
Parameter
Commercial Supply
Voltage
Supply Voltage
Input High Voltage
Commercial
Input Low Voltage
Operating Temperature
Industrial
Min.
4.5
0
2.0
—
-40
Typ.
5.0
0
—
—
—
Max. Unit
5.5
0
—
0.8
85
V
V
V
V
°C
2753 tbl 03
NOTE:
2753 tbl 01
1.Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5.0V
±
10%, T
A
= -40°C to +85°C)
IDT72103
IDT72104
Industrial
t
A
= 35, 50ns
Symbol
I
LI
(1)
I
LO
(2)
V
OH
V
OL
I
CC1
(3)
I
CC2
(3,6)
Parameter
Input Leakage Current (Any Input)
Output Leakage Current
Output Logic "1" Voltage,
I
OUT
= –2mA
(4)
Output Logic "0" Voltage,
I
OUT
= 8mA
(5)
Active Power Supply Current
Standby Current
(
R
=
W
=
RS
=
FL
/
RT
= V
IH
)
(SOCP = SICP = V
IL
)
Power Down Current
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
90
8
Max.
1
10
—
0.4
140
12
Unit
µA
µA
V
V
mA
mA
I
CC3
(3,6)
—
—
2
mA
2753 tbl 06
NOTES:
1. Measurements with 0.4
≤
V
IN
≤
V
CC
.
2.
R
≥
V
IH
, SOCP
≤
V
IL
, 0.4
≤
V
OUT
≤
V
CC
.
3. Tested with outputs open (I
OUT
= 0).
4. For SO, I
OUT
= –8mA.
5. For SO, I
OUT
=16mA.
6. SOCP = SICP
≤
0.2V; other Inputs = V
CC
- 0.2V.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
10
12
Unit
pF
pF
2753 tbl 02
5V
1.1KΩ
D.U.T.
680Ω
30pF*
2753 drw 04
NOTE:
1. This parameter is sampled and not 100% tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2753 tbl 07
or equivalent circuit
Figure 1. Ouput Load
*Including jig and scope capacitances
4
IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2,048 x 9 AND 4,096 x 9
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5.0V
±
10%, T
A
= -40°C to +85°C)
Industrial
IDT72103L35
IDT72103L50
IDT72104L35
IDT72104L50
Min.
Max.
Min.
Max.
—
22.2
—
15
—
50
—
40
—
50
—
40
—
10
35
45
5
5
—
5
18
0
45
35
10
45
35
35
10
—
—
20
20
20
45
35
35
10
—
—
—
—
—
35
—
—
—
—
35
35
—
—
—
—
—
20
—
—
—
—
—
—
—
—
—
—
45
45
—
—
—
—
—
—
—
35
30
30
45
45
—
30
30
45
45
—
—
15
50
65
15
10
—
5
20
0
50
40
10
50
40
40
10
—
—
20
20
20
50
40
40
10
—
—
—
—
—
40
—
—
—
—
40
50
—
—
—
—
—
30
—
—
—
—
—
—
—
—
—
—
65
65
—
—
—
—
—
—
—
50
45
45
65
65
—
45
45
65
65
—
Symbol
Parameter
f
S
Parallel Shift Frequency
f
SOCP
Serial-Out Shift Frequency
f
SICP
Serial-In Shift Frequency
PARALLEL-OUTPUT MODE TIMINGS
t
A
Access Time
t
RR
Read Recovery Time
t
RPW
Read Pulse Width
t
RC
Read Cycle Time
t
WLZ
Write Pulse LOW to Data Bus at Low-Z
(1)
t
RLZ
Read Pulse LOW to Data Bus at Low-Z
(1)
t
RHZ
Read Pulse HIGH to Data Bus at High-Z
(1)
t
DV
Data Valid from Read Pulse HIGH
PARALLEL-INPUT MODE TIMINGS
t
DS
Data Set-up Time
t
DH
Data Hold Time
t
WC
Write Cycle Time
t
WPW
Write Pulse Width
t
WR
Write Recovery Time
RESET TIMINGS
t
RSC
Reset Cycle Time
t
RS
Reset Pulse Width
t
RSS
Reset Set-up Time
t
RSR
Reset Recovery Time
RESET TO FLAG TIMINGS
t
RSF1
Reset to
EF
,
AEF
, and
EF+1
LOW
t
RSF2
Reset to
HF
,
FF
, and
FF-1
LOW
RESET TO OUTPUT TIMINGS – SERIAL MODE ONLY
t
RSQL
Reset Going LOW to Q
0-8
LOW
t
RSQH
Reset Going HIGH to Q
0-8
HIGH
t
RSDL
Reset Going LOW to D
0-8
LOW
RETRANSMIT TIMINGS
t
RTC
Retransmit Cycle Time
t
RT
Retransmit Pulse Width
t
RTS
Retransmit Set-up Time
t
RTR
Retransmit Recovery Time
t
RTF
Retransmit to Flags
PARALLEL MODE FLAG TIMINGS
t
REF
Read LOW to
EF
LOW
t
RFF
Read HIGH to
FF
HIGH
t
RF
Read HIGH to Transitioning
HF
,
AEF
and
FF-1
t
RE
Read LOW to
EF+1
LOW
t
RPE
Read Pulse Width after
EF
HIGH
t
WEF
Write HIGH to
EF
HIGH
t
WFF
Write LOW to
FF
LOW
t
WF
Write LOW to Transitioning
HF
,
AEF
and
FF-1
t
WE
Write HIGH to
EF+1
HIGH
t
WPF
Write Pulse Width after
FF
HIGH
NOTE:
1. Values guaranteed by design, not tested.
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Timing
Figure
—
—
—
4
4
4
4
15
4
4
4
3
3
3
3
3
2,18
2,18
2,18
2,17,18
2
2
18
18
17
5
5
5
5
5
6
7
8,9,10
11
15
6
7
8,9,10
11
16
2753 tbl 08
5
以拆会友
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
