MB96345/346, MB96F345
MB96F346/F347/F348
F
2
MC-16FX, MB96340 Series,
16-bit
Proprietary Microcontroller Datasheet
MB96340 series is based on Cypress advanced 16FX architecture (16-bit with instruction pipeline for RISC-like performance). The
CPU uses the same instruction set as the established 16LX series - thus allowing for easy migration of 16LX Software to the new
16FX products. 16FX improvements compared to the previous generation include significantly improved performance - even at the
same operation frequency, reduced power consumption and faster start-up time.
For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 56MHz
operation frequency from an external 4MHz resonator. The result is a minimum instruction cycle time of 17.8ns going together with
excellent EMI behavior. An on-chip clock modulation circuit significantly reduces emission peaks in the frequency spectrum. The
emitted power is minimized by the on-chip voltage regulator that reduces the internal CPU voltage. A flexible clock tree allows to select
suitable operation frequencies for peripheral resources independent of the CPU speed.
MB96F345 : These devices are under development and specification is preliminary. These products under development may
change its specification without notice.
Cypress Semiconductor Corporation
Document Number: 002-04579 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 4, 2016
MB96340 Series
Features
Feature
Technology
■
0.18m CMOS
■
F
2
MC-16FX CPU
■
Up to 56 MHz internal, 17.8 ns instruction cycle time
■
Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different
Description
CPU
addressing modes; barrel shift; variety of pointers)
■
8-byte instruction execution queue
■
Signed multiply (16-bit
×
16-bit) and divide (32-bit/16-bit) instructions available
■
On-chip PLL clock multiplier (x1 - x25, x1 when PLL stop)
■
3 MHz - 16 MHz external crystal oscillator clock (maximum frequency when using ceramic resonator depends
on Q-factor).
■
Up to 56 MHz external clock for devices with fast clock input feature
System clock
■
32-100 kHz subsystem quartz clock
■
100kHz/2MHz internal RC clock for quick and safe startup, oscillator stop detection, watchdog
■
Clock source selectable from main- and subclock oscillator (part number suffix “W”) and on-chip RC
oscillator, independently for CPU and 2 clock domains of peripherals.
■
Low Power Consumption - 13 operating modes : (different Run, Sleep, Timer modes, Stop mode)
■
Clock modulator
On-chip voltage regulator
Low voltage reset
Code Security
Memory Patch Function
DMA
Interrupts
■
Internal voltage regulator supports reduced internal MCU voltage, offering low EMI and low power
consumption figures
■
Reset is generated when supply voltage is below minimum.
■
Protects ROM content from unintended read-out
■
Replaces ROM content
■
Can also be used to implement embedded debug support
■
Automatic transfer function independent of CPU, can be assigned freely to resources
■
Fast Interrupt processing
■
8 programmable priority levels
■
Non-Maskable Interrupt (NMI)
■
Three independent clock timers (23-bit RC clock timer, 23-bit Main clock timer,
Timers
17-bit Sub clock timer)
■
Watchdog Timer
■
Supports CAN protocol version 2.0 part A and B
■
ISO16845 certified
■
Bit rates up to 1 Mbit/s
■
32 message objects
CAN
■
Each message object has its own identifier mask
■
Programmable FIFO mode (concatenation of message objects)
■
Maskable interrupt
■
Disabled Automatic Retransmission mode for Time Triggered CAN applications
■
Programmable loop-back mode for self-test operation
■
Full duplex USARTs (SCI/LIN)
USART
■
Wide range of baud rate settings using a dedicated reload timer
■
Special synchronous options for adapting to different synchronous serial protocols
■
LIN functionality working either as master or slave LIN device
Document Number: 002-04579 Rev. *A
Page 2 of 109
MB96340 Series
Feature
I
2
C
■
Up to 400 kbps
Description
■
Master and Slave functionality, 8-bit and 10-bit addressing
■
SAR-type
A/D converter
■
10-bit resolution
■
Signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion
mode, activation by software, external trigger or reload timer
A/D Converter Reference Volt-
■
2 independent positive A/D converter reference voltages available
age switch
■
16-bit wide
Reload Timers
■
Prescaler with 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
of peripheral clock frequency
■
Event count function
Free Running Timers
■
Signals an interrupt on overflow, supports timer clear upon match with Output Compare (0, 4), Prescaler
with 1, 1/2
1
, 1/2
2
, 1/2
3
, 1/2
4
, 1/2
5
, 1/2
6
, 1/2
7
,1/2
8
of peripheral clock frequency
■
16-bit wide
Input Capture Units
■
Signals an interrupt upon external event
■
Rising edge, falling edge or rising & falling edge sensitive
■
16-bit wide
Output Compare Units
■
Signals an interrupt when a match with 16-bit I/O Timer occurs
■
A pair of compare registers can be used to generate an output signal.
■
16-bit down counter, cycle and duty setting registers
■
Interrupt at trigger, counter borrow and/or duty match
Programmable Pulse Genera-
■
PWM operation and one-shot operation
tor
■
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and Reload timer overflow
as clock input
■
Can be triggered by software or reload timer
■
Can be clocked either from sub oscillator (devices with part number suffix “W”), main oscillator or from the
RC oscillator
Real Time Clock
■
Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock calibration)
■
Read/write accessible second/minute/hour registers
■
Can signal interrupts every half second/second/minute/hour/day
■
Internal clock divider and prescaler provide exact 1s clock
■
Edge sensitive or level sensitive
External Interrupts
■
Interrupt mask and pending bit per channel
■
Each available CAN channel RX has an external interrupt for wake-up
■
Selected USART channels SIN have an external interrupt for wake-up
■
Disabled after reset
Non Maskable Interrupt
■
Once enabled, can not be disabled other than by reset.
■
Level high or level low sensitive
■
Pin shared with external interrupt 0.
■
8-bit or 16-bit bidirectional data
■
Up to 24-bit addresses
■
6 chip select signals
External bus interface
■
Multiplexed address/data lines
■
Wait state request
■
External bus master possible
■
Timing programmable
Document Number: 002-04579 Rev. *A
Page 3 of 109
MB96340 Series
Feature
thresholds
Description
■
Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined
Alarm comparator
■
Threshold voltages defined externally or generated internally
■
Status is readable, interrupts can be masked separately
■
Virtually all external pins can be used as general purpose I/O
■
All push-pull outputs (except when used as I2C SDA/SCL line)
■
Bit-wise programmable as input/output or peripheral signal
■
Bit-wise programmable input enable
■
Bit-wise programmable input levels: Automotive / CMOS-Schmitt trigger / TTL (TTL levels not supported
I/O Ports
by all devices)
■
Bit-wise programmable pull-up resistor
■
Bit-wise programmable output driving strength for EMI optimization
Packages
■
100-pin plastic QFP and LQFP
■
Supports automatic programming, Embedded Algorithm
■
Write/Erase/Erase-Suspend/Resume commands
■
A flag indicating completion of the algorithm
■
Number of erase cycles: 10,000 times
Flash Memory
■
Data retention time: 20 years
■
Erase can be performed on each sector individually
■
Sector protection
■
Flash Security feature to protect the content of the Flash
■
Low voltage detection during Flash erase
Document Number: 002-04579 Rev. *A
Page 4 of 109
MB96340 Series
Contents
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Product Lineup.............................................................
6
Block Diagram..............................................................
8
Pin Assignments
.......................................................... 9
Pin Function Description
.......................................... 11
Pin Circuit Type..........................................................
13
I/O Circuit Type...........................................................
14
Memory Map
............................................................... 17
User ROM Memory Map
for
Flash Devices
........... 19
User ROM Memory Map for Mask ROM Devices.....
22
Serial Programming Communication Interface.......
23
I/O Map
........................................................................ 24
Interrupt Vector Table
................................................ 52
Handling Devices
....................................................... 56
Latch-up prevention ..................................................... 56
Unused pins handling .................................................. 56
External clock usage.................................................... 56
Unused sub clock signal .............................................. 57
Notes on PLL clock mode operation ............................ 57
Power supply pins (VCC/VSS)..................................... 57
Crystal oscillator and ceramic resonator circuit ........... 57
Turn on sequence of power supply to A/D converter and
analog inputs................................................................ 58
13.9 Pin handling when not using the A/D converter ............ 58
13.10Notes on Power-on....................................................... 58
13.11Stabilization of power supply voltage ........................... 58
13.12Serial communication ................................................... 58
13.13Handling of Data Flash ................................................. 58
14.
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
15.
16.
17.
Electrical Characteristics
........................................... 59
Absolute Maximum Ratings .......................................... 59
Recommended Operating Conditions........................... 61
DC characteristics......................................................... 62
AC Characteristics ........................................................ 71
Analog Digital Converter ............................................... 89
Alarm Comparator......................................................... 93
Low Voltage Detector Characteristics........................... 95
Flash Memory Program/erase Characteristics.............. 97
Example Characteristics
............................................ 98
Package Dimension MB96(F)34x LQFP 100P.........
102
Package Dimension MB96(F)34x QFP 100P
........... 103
18. Ordering Information
................................................ 104
18.1 MCU with CAN Controller ........................................... 104
18.2 MCU without CAN Controller ...................................... 106
19.
20.
Revision History........................................................
107
Main Changes in this Edition...................................
109
Document History ................................................................. 50
Document Number: 002-04579 Rev. *A
Page 5 of 109
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