TSPC750IP
Processor and Cache Module
DESCRIPTION
The Processor and Cache Module (PCM) is a 17 x 17 pin grid
array (PGA) circuit assembly which combines a PowerPCt
microprocessor and SRAM components into a CPU subsys-
tem. The PCM provides a standard mechanical, electrical, and
functional interface which can be socketed on a computer sys-
tem board and allows many combinations of processors and
optional components to be easily interchanged. This docu-
ment describes the general characteristics for a module con-
sisting of a single PowerPCt microprocessor and two SRAM
devices for L2 cache. The PCM packaging and PGA signal
definition also accomodates single processors without SRAM,
and multiple processors.
The PCM consists of an epoxy–glass (FR4) substrate which
adapts a processor in a ceramic ball grid array (CBGA) pac-
kage with 50 mil spacing to a 288–pin PGA with 100 mil spac-
ing that can be easily socketed and hence, easily upgraded.
The FR4 substrate can be extended beyond the area of the 17
x 17 pin grid array to provide an interconnect area for SRAM
components configured as closely coupled L2 cache. The
resulting PCM provides numerous flexible configurations of
processor and cache for various price/performance system
designs.
FR4 PCM on PGA 288 Interposer
I
N
60x Address
T
60x Data
E
R
60x Control
P
O
S
PLL_CFG
E
R
P
I
N
S
TSPC750
Processor
L2 Addr
L2 Data
L2 Control
L2–Cache
Memory
Chips
VID
PID
General
Support
Circuits
Simplified Block Diagram
April 1999
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TSPC750IP
1. PIN ASSIGNEMENT
Figure 1 (in part A) shows the pinout of the PCM as viewed from the top surface. Part B shows the side profile of the module to indicate
the direction of the top surface view.
Part A
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Not to Scale
Part B
CBGA Substrate
Microprocessor Die
TQFP Packaged SRAM
View
2/17
ÎÎÎÎÎÎÎÎÎ
FR4 PCM
Figure 117 x 17 PGA Processor + Cache Module
TSPC750IP
2. PINOUT LISTING
Table 1 provides the pinout listing for the 17 x 17 PGA PCM. This pinout is the superset of all 17 x 17 PCMs and should be followed for
maximum interchangeability between modules; however, particular implementations may not connect all signals between the PGA
pins and the PowerPC microprocessor. See the individual part number specifications for specific pinouts by part number.
Table 1. Pinout Listing for the 17 x 17 PGA Module
Signal Name
A[0–31]
Pin Number
F13, E1, D17, F3, E16,F1, E17, G5, F15, G4, G13, G3,
F17, G2, G14, G1, G15, H1, G16, H3, G17, J1, H13, H5,
H15, J2, H17, J3, J13, L1, K13, M1
K3
L3
E6, C4, C5, A4
C8
A8
K5
A11
J5
E13
E8
A17
E2
A6
C9
E9
E7, B5
L17
J15
K1
R15
J4
P13, N12, T15, U15, R13, U14, N10,P11, T11, U11, R10,
U10, U9, T9, N9,P9, R9, U8, R8, U7, N8, P7, T7,U6, R7,
R6, N7, U5, T5, U4, R5,U3
L16, K15, M17, L14, N17, M15, N16, L13, M13, N15, P17,
R17, N14, P15, R16, U16, R14, N11, T13, R12, U13, R11,
U12, N3, P3, N4, R2, T1, T3, R4, P5, N6
Active
High
I/O
I/O
AACK
ABB
AP[0–3]
APE
ARRAY_WR
2
ARTRY
AVDD
BG
BG2
BR
BR2
CI
CLK_OUT
CKSTP_IN
CKSTP_OUT
CSE0–CSE1
1
DBB
DBDIS
DBG
DBG2
DBWO
DH[0–31]
Low
Low
High
Low
Low
Low
High
Low
Low
Low
Low
Low
—
Low
Low
High
Low
Low
Low
Low
Low
High
Input
I/O
I/O
Output
Input
I/O
Input
Input
Input
Output
Output
Output
Output
Input
Output
Output
I/O
Input
Input
Input
Input
I/O
DL[0–31]
High
I/O
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TSPC750IP
Table 1. Pinout Listing for the 17 x 17 PGA Module (cont’d)
Signal Name
DP[0–7]
DPE
DRTRY
DRVMOD[0–1]
GBL
GND
Pin Number
L4, N1, M3, N2, P1, L5, R1, M5
B7
J17
E3, D3
F5
B4, B8, B10, B14, D2, D6, D12, D16,F4, F6, F8, F10, F12,
F14, G7, G9, G11, H2, H6, H8, H10, H12, H16, J7, J9, J11,
K2, K6, K8, K10, K12, K16, L7, L9, L11, M4, M6, M8, M10,
M12, M14, P2, P6, P12, P16, T4, T8, T10, T14
D9
B9
E14
U17
D11
B11
A7
E10
D15
D7
N13
B2, B6, B12, B16, D4, D8, D10, D14, F2, F9, F16, H4,
H14, J6, J12, K4, K14, M2, M9, M16, P4, P8, P10, P14,
T2, T6, T12, T16
U1, U2, R3
A9, A10, A13, C11
E5
N5
D5
A3
C1
L2
B17
Active
High
Low
Low
—
Low
Low
I/O
I/O
Output
Input
Input
I/O
Input
HALTED
HRESET
INT
INT2
LSSD_MODE
2
L1_TSTCLK
2
L2_INT
L2_TSTCLK
2
MCP
NAP_RUN
NC
5
OVDD
3
High
Low
Low
Low
Low
—
High
—
Low
High
—
High
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
–
Input
PID[0–2]
PLL_CFG[0–3]
QACK
QREQ
RSRV
SCLK
SDATA
SHD
SMI
High
High
Low
Low
Low
—
—
Low
Low
I/O
Input
Input
Output
Output
Input
I/O
I/O
Input
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TSPC750IP
Table 1. Pinout Listing for the 17 x 17 PGA Module (cont’d)
Signal Name
SRESET
SYSCLK
SYSCLK2
TA
TBEN
TBST
TC[0–2]
4
TCK
TDI
TDO
TEA
TLBISYNC
TMS
TRST
TSIZ[0–2]
TS
TT[0–4]
VDD
3
D13
C10
T17
J16
E4
E12
C6, A5, C7
C12
B13
A14
J14
C15
C13
A12
E11, A15, B15
L15
A16, C14, C16, C17, E15
F7, F11, G6, G8, G10, G12, H7, H9, H11, J8, J10, K7, K9,
K11, L6, L8, L10, L12, M7, M11
B1, C2, A2, B3, C3
D1
K17
Pin Number
Active
Low
—
—
Low
High
Low
High
—
High
High
Low
Low
High
Low
High
Low
High
High
I/O
Input
Input
Input
Input
Input
I/O
Output
Input
Input
Output
Input
Input
Input
Input
I/O
I/O
I/O
Input
VID[0–4]
WT
XATS
1
Notes:
High
Low
Low
Input
Output
Output
1. Not recommended for new designs.
2. These are test signals for factory use only and must be pulled up to Vdd for normal machine operation.
3. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
4. TC2 defined for PowerPC 604™–class processors only.
5. These signals are undefined and must be left disconnected.
Many of the PCM signals have the same definition and timing as that of the attached processor. The actual signals present vary
depending upon the type of the PowerPC microprocessor used; refer to the corresponding processor hardware specifications for
details.
The PCM implements several signals that are not part of the PowerPC 60x bus specification, nor of any particular PowerPC proces-
sor. These pins are unique to the PCM and are used to set operational parameters or indicate the features the PCM provides. Table 2
describes the functions of the signals provided for identification or configuration of the PCM.
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