Crystal Clock Oscillators
22SMOP
(+2.8V, +3.0V or +3.3V PROGRAMMABLE MODELS)
22SMOP
Actual Size
STANDARD SMD CLOCK OSCILLATORS
using PLL technology
Specifications
22SMOP
※1
0.5 MHz to 200.0000 MHz
22SMOP(A) :
±100
ppm over -20˚C to
＋75˚C
22SMOP(B) :
±50
ppm over -20˚C to
＋75˚C
22SMOP(AW) :
±100
ppm over -40˚C to
＋85˚C
-20˚C to
＋75˚C
(standard)
-40˚C to
＋85˚C
(W)
＋2.8V ±5%, ＋3.0V ±5%
or
＋3.3V ±5%
V
IH
: 80%V
DD
min.
V
IL
: 20%V
DD
max.
※2
-0.3V to
＋7.0V
DC
-55˚C to
＋125˚C
30 mA max. (Pin #1 = Open or V
IH
)
100
μA
max. (Pin #1=V
IL
)
45% to 55% at 50%V
DD
level (0.5MHz to 80.00MHz)
40% to 60% at 50%V
DD
level (80.00MHz to 200.00MHz)
7 ns max. (0.5MHz to 100.000MHz)
4 ns max. (100.000MHz to 200.000MHz)
V
OL
: 10%V
DD
max.
V
OH
: 90%V
DD
min.
15 pF max. (CMOS)
150 ns max.
10 ms max.
10 ms max.
±5
ppm max. at
＋25˚C ±3˚C
for first year
200 ps : Cycle to cycle
250 ps : Peak to peak
＋250˚C ±10˚C
for 10 seconds
＋170˚C ±10˚C
for 1 to 2 minutes (preheating)
STANDARD SPECIFICATIONS
Item
Generic part number
Frequency range
Frequency stability
over all conditions
Operating Conditions
Operating temperature
CLK OSC
Input voltage (V
DD
)
Stand-by control voltage (Pin#1)
22SMOP
2.5±0.1
#4
#3
2.0±0.1
#1
#2
1.0±0.1
Absolute Max. Ratings
Supply voltage
Storage temperature
Input current
Stand-by current
※2
Output (-20˚C to
＋75˚C)
Symmetry
Rise and fall times
(10%V
DD
to 90%V
DD
level)
"0" level
"1" level
Load
Disable delay time
Enable delay time
Startup time
Aging
Jitter
Reflow condition
0.8 0.9 0.8
#1
A
D
C
#4
PIN
1
2
3
4
#3
CONNECTION
"L"
OPEN or "H"
GND
Z
OUTPUT
V
DD
Z : high impedance
B
#2
0.7 0.6 0.7
TF
＊
The terminals (A, B, C & D)
not to be connected.
OUTPUT WAVEFORM
TR
V
OH
("1"Level)
V
DD
90% or 80% V
DD
50% V
DD
V
OL
("0"Level)
GND
10% or 20% V
DD
OV DC
T
Symmetry=t/T×100(%)
(※1) Final exact part number to be determined with frequency, frequency stability, operating temperature and input voltage.
e.g. 22SMOP(3.3VA) 125.000 MHz.
(※2) Internal crystal oscillation to be halted (Pin #1=V
IL
).
t
PACKAGE DATA
Item
Package
22SMOP
Metal
Ceramic
AuSn
Tungsten (metalized)
Gold / Nickel
(surface) / (under)
Compliant (Pb-free)
TEST CIRCUIT
Test Point
V
DD
A
#4
V
DD
Lid
Base
Sealing
Terminal
CL
#3
OUTPUT
GND
DC Power
Supply
0.01μ
F∼0.1μF
V
TRI-STATE
E/D SW
#1
#2
Terminal plating
RoHS
TAPE SPECIFICATIONS
4.0±0.1
0.1
φ
1.5
+-
0
1.75±0.1
D
A
J
M
B
F
C
L
2.0±0.1
CL : including fixture and probe capacitance.
SOLDERING PATTERN
1.1
0.7
1.1
0.5
0.9
0.01μF
∼
0.1μF
1.8
M Reel Dia. Qty/Reel
2000pcs
2.8 2.3 8.0 3.5 4.0 1.0 0.25 1.1
180 1000pcs
A
B
C
D
F
J
L
76
0.9
FPGA/CPLD
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