CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9, 1K x 9

Integrated Device Technology, Inc.

IDT7200L

IDT7201LA

IDT7202LA

FEATURES:

•

First-In/First-Out dual-port memory

256 x 9 organization (IDT7200)

512 x 9 organization (IDT7201)

1K x 9 organization (IDT7202)

Low power consumption

— Active: 770mW (max.)

—Power-down: 2.75mW (max.)

Ultra high speed—12ns access time

Asynchronous and simultaneous read and write

Fully expandable by both word depth and/or bit width

Pin and functionally compatible with 720X family

Status Flags: Empty, Half-Full, Full

Auto-retransmit capability

High-performance CEMOS™ technology

Military product compliant to MIL-STD-883, Class B

Standard Military Drawing #5962-87531, 5962-89666,

5962-89863 and 5962-89536 are listed on this function

Industrial temperature range (-40oC to +85oC) is

available, tested to military electrical specifications

DESCRIPTION:

The IDT7200/7201/7202 are dual-port memories that load

and empty data on a first-in/first-out basis. The devices use

Full and Empty flags to prevent data overflow and underflow

and expansion logic to allow for unlimited expansion capability

in both word size and depth.

The reads and writes are internally sequential through the

use of ring pointers, with no address information required to

load and unload data. Data is toggled in and out of the devices

through the use of the Write (

W

) and Read (

R

) pins.

The devices utilizes a 9-bit wide data array to allow for

control and parity bits at the user’s option. This feature is

especially useful in data communications applications where

it is necessary to use a parity bit for transmission/reception

error checking. It also features a Retransmit (

RT

) capability

that allows for reset of the read pointer to its initial position

when

RT

is pulsed low to allow for retransmission from the

beginning of data. A Half-Full Flag is available in the single

device mode and width expansion modes.

The IDT7200/7201/7202 are fabricated using IDT’s high-

speed CMOS technology. They are designed for those

applications requiring asynchronous and simultaneous read/

writes in multiprocessing and rate buffer applications. Military

grade product is manufactured in compliance with the latest

revision of MIL-STD-883, Class B.

•

FUNCTIONAL BLOCK DIAGRAM

DATA INPUTS

(D

0

–D

8

)

W

WRITE

CONTROL

WRITE

POINTER

RAM

ARRAY

256 x 9

512 x 9

1024 x 9

READ

POINTER

R

READ

CONTROL

THREE-

STATE

BUFFERS

DATA OUTPUTS

(Q

0

–Q

8

)

RS

RESET

LOGIC

FLAG

LOGIC

EF

FF

XO

/

HF

FL

/

RT

XI

EXPANSION

LOGIC

2679 drw 01

The IDT logo is a trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

DECEMBER 1996

DSC-2679/7

5.03

1

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

D

3

D

8

W

D

8

D

3

D

2

D

1

D

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

P28-1,

P28-2,

D28-1,

D28-3,

E28-2,

SO28-3

28

27

26

25

24

23

22

21

20

19

18

17

16

15

V

CC

D

4

D

5

D

6

D

7

4 3 2

D

2

D

1

D

0

5

6

7

8

9

10

11

12

13

1

32 31 30

29

28

27

26

25

24

23

22

21

D

6

D

7

NC

FL

/

RT

XI

FF

Q

0

Q

1

Q

2

Q

3

Q

8

GND

FL

/

RT

RS

EF

XO

/

HF

Q

7

Q

6

Q

5

Q

4

XI

FF

Q

0

Q

1

NC

Q

2

J32-1

&

L32-1

D

5

W

PIN CONFIGURATIONS

INDEX

NC

V

CC

D

4

RS

EF

XO

/

HF

Q

7

Q

6

14 15 16 17 18 19 20

GND

NC

R

2679 drw 02a

Q

3

Q

8

R

Q

4

Q

5

2679 drw 02b

DIP/SOIC/CERPACK

TOP VIEW

NOTE:

1. CERPACK (E28-2) and 600-mil-wide DIP (P28-1 and D28-1) not available

for 7200.

LCC/PLCC

TOP VIEW

NOTE:

1. LCC (L32-1) not available for 7200.

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

V

TERM

Terminal Voltage

with Respect

to GND

T

A

Operating

Temperature

T

BIAS

Temperature

Under Bias

T

STG

Storage

Temperature

I

OUT

DC Output

Current

(1)

RECOMMENDED DC OPERATING

CONDITIONS

Symbol

V

CCM

V

CCC

GND

V

IH(1)

V

IH(1)

Parameter

Military Supply

Voltage

Commercial Supply

Voltage

Supply Voltage

Input High Voltage

Commercial

Input High Voltage

Mlitary

Input Low Voltage

Commercial and

Military

Min.

4.5

0

2.0

2.2

—

Typ.

5.0

0

—

Max.

5.5

0

—

0.8

Unit

V

Com’l.

Mil.

Unit

–0.5 to +7.0 –0.5 to +7.0 V

0 to +70

–55 to +125

°C

mA

–55 to +125 –65 to +135

–55 to +125 –65 to +155

50

V

IL(2)

NOTE:

2679 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliabilty.

NOTE:

1. V

IH

= 2.6V for

XI

input (commercial).

V

IH

= 2.8V for

XI

input (military).

2. 1.5V undershoots are allowed for 10ns once per cycle.

2679 tbl 03

CAPACITANCE

(T

A

= +25°C, f = 1.0 MHz)

Symbol

C

IN

C

OUT

Parameter

(1)

Input Capacitance

Output Capacitance

Condition

V

IN

= 0V

V

OUT

= 0V

Max.

8

Unit

pF

2679 tbl 02

NOTE:

1. This parameter is sampled and not 100% tested.

5.03

2

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS

(Commercial: V

CC

= 5.0V±10%, T

A

= 0°C to +70°C; Military: V

CC

= 5.0V±10%, T

A

= –55°C to +125°C)

IDT7200L

IDT7201LA

IDT7202LA

Commercial

t

A

= 12, 15, 20 ns

Symbol

I

LI(1)

I

LO(2)

V

OH

V

OL

I

CC1(3)

I

CC2(3)

I

CC3

(L)

(3)

Parameter

Input Leakage Current (Any Input)

Output Leakage Current

Output Logic “1” Voltage I

OH

= –2mA

Output Logic “0” Voltage I

OL

= 8mA

Active Power Supply Current

Standby Current (

R

=

W

=

RS

=

FL

/

RT

=V

IH

)

Power Down Current (All Input = V

CC

- 0.2V)

Min.

–1

–10

2.4

—

Typ.

—

Max.

1

10

—

0.4

125

(4)

15

0.5

IDT7200L

IDT7201LA

IDT7202LA

Military

t

A

= 20 ns

Min.

–10

2.4

—

Typ.

—

Max.

10

—

0.4

140

(4)

20

0.9

IDT7200L

IDT7201LA

IDT7202LA

Commercial

t

A

= 25, 35 ns

Min.

–1

–10

2.4

—

Typ. Max. Unit

—

1

10

—

0.4

15

0.5

µA

V

mA

2679 tbl 05

04

125

(4)

mA

NOTES:

1. Measurements with 0.4

≤

V

IN

≤

V

CC

.

2.

R

≥

V

IH

, 0.4

≤

V

OUT

≤

V

CC

.

3. I

CC

measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

DC ELECTRICAL CHARACTERISTICS (Continued)

(Commercial: V

CC

= 5.0V±10%, T

A

= 0°C to +70°C; Military: V

CC

= 5.0V±10%, T

A

= –55°C to +125°C)

IDT7200L

IDT7201LA

IDT7202LA

Military

t

A

= 30, 40 ns

Symbol

I

LI

(1)

IDT7200L

IDT7201LA

IDT7202LA

Commercial

t

A

= 50 ns

Min.

–1

–10

2.4

—

Typ. Max.

—

50

5

—

1

10

—

0.4

80

8

0.5

IDT7200L

IDT7201LA

IDT7202LA

Military

t

A

= 50, 65, 80, 120 ns

Min.

–10

2.4

—

Typ.

—

70

8

—

Max. Unit

10

—

0.4

100

15

0.9

µA

V

mA

2679 tbl 05

Parameter

Input Leakage Current (Any Input)

Output Leakage Current

Output Logic “1” Voltage I

OH

= –2mA

Output Logic “0” Voltage I

OL

= 8mA

Active Power Supply Current

Standby Current (

R

=

W

=

RS

=

FL

/

RT

=V

IH

)

Power Down Current (All Input = V

CC

- 0.2V)

Min.

–10

2.4

—

Typ.

—

Max.

10

—

0.4

140

(4)

20

0.9

I

LO(2)

V

OH

V

OL

I

CC1(3)

I

CC2(3)

I

CC3

(L)

(3)

NOTES:

1. Measurements with 0.4

≤

V

IN

≤

V

CC

.

2.

R

≥

V

IH

, 0.4

≤

V

OUT

≤

V

CC

.

3. I

CC

measurements are made with outputs open (only capacitive loading).

4. Tested at f = 20MHz.

5.03

3

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Commercial: V

CC

= 5.0V±10%, T

A

= 0°C to +70°C; Military: V

CC

= 5.0V±10%, T

A

= –55°C to +125°C)

Commercial

7200L12

7200L15

7201LA12 7201LA15

7202LA12 7202LA15

Symbol Parameter

t

S

t

RC

t

A

t

RR

t

RPW

t

RLZ

t

WLZ

t

DV

t

RHZ

t

WC

t

WPW

t

WR

t

DS

t

DH

t

RSC

t

RS

t

RSS

t

RSR

t

RTC

t

RT

t

RTS

t

RTR

t

EFL

t

RTF

t

REF

t

RFF

t

RPE

t

WEF

t

WFF

t

WHF

t

RHF

t

WPF

t

XOL

t

XOH

t

XI

t

XIR

t

XIS

Shift Frequency

Read Cycle Time

Access Time

Read Recovery Time

Read Pulse Width

(2)

(3)

(3, 4)

Com'l & Mil.

7200L20

7201LA20

7202LA20

—

30

—

10

20

5

—

30

20

10

12

0

30

20

10

30

20

10

—

20

—

20

—

20

10

33.3

—

20

—

15

—

30

20

—

20

30

—

20

—

Com'l

Military

Com'l

7200L35

7201LA35

7202LA35

—

45

—

10

35

5

10

5

—

45

35

10

18

0

45

35

10

45

35

10

—

35

—

35

—

35

10

22.2 MHz

—

35

—

20

—

45

30

—

30

45

—

35

—

ns

2679 tbl 06

7200L25

7200L30

7201LA25 7201LA30

7202LA25 7202LA30

—

35

—

10

25

5

—

35

25

10

15

0

35

25

10

35

25

10

—

25

—

25

—

25

10

28.5

—

25

—

18

—

35

25

—

25

35

—

25

—

40

—

10

30

5

—

40

30

10

18

0

40

30

10

40

30

10

—

30

—

30

—

30

10

25

—

30

—

20

—

40

30

—

30

40

—

30

—

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

—

20

—

8

12

3

5

(3)

50

—

12

—

12

—

12

17

20

12

14

—

12

14

17

—

12

—

25

—

10

15

5

—

25

15

10

11

0

25

15

10

25

15

10

—

15

—

15

—

15

10

40

—

15

—

15

—

25

15

—

15

25

—

15

—

Read Pulse Low to Data Bus at Low Z

Data Valid from Read Pulse High

Write Pulse High to Data Bus at Low Z

Read Pulse High to Data Bus at High Z

Write Cycle Time

Write Pulse Width

(2)

Write Recovery Time

Data Set-up Time

Data Hold Time

Reset Cycle Time

Reset Pulse Width

(2)

Reset Set-up Time

(3)

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width

(2)

Retransmit Set-up Time

(3)

Retransmit Recovery Time

Reset to Empty Flag Low

Retransmit Low to Flags Valid

Read Low to Empty Flag Low

Read High to Full Flag High

Read Pulse Width after

EF

High

Write High to Empty Flag High

Write Low to Full Flag Low

Write Low to Half-Full Flag Low

Read High to Half-Full Flag High

Write Pulse Width after

FF

High

Read/Write to

XO

Low

Read/Write to

XO

High

—

20

12

8

9

0

20

12

8

20

12

8

—

12

—

12

—

12

8

t

HFH,FFH

Reset to Half-Full and Full Flag High

XI

Pulse Width

(2)

XI

Recovery Time

XI

Set-up Time

NOTES:

1. Timings referenced as in AC Test Conditions.

2. Pulse widths less than minimum value are not allowed.

3. Values guaranteed by design, not currently tested.

4. Only applies to read data flow-through mode.

5.03

4

IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1K x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS

(1)

(Continued)

(Commercial: V

CC

= 5.0V±10%, T

A

= 0°C to +70°C; Military: V

CC

= 5.0V±10%, T

A

= –55°C to +125°C)

Military

7200 L40

7201LA40

7202LA40

Symbol

t

S

t

RC

t

A

t

RR

t

RPW

t

RLZ

t

WLZ

t

DV

t

RHZ

t

WC

t

WPW

t

WR

t

DS

t

DH

t

RSC

t

RS

t

RSS

t

RSR

t

RTC

t

RT

t

RTS

t

RTR

t

EFL

t

RTF

t

REF

t

RFF

t

RPE

t

WEF

t

WFF

t

WHF

t

RHF

t

WPF

t

XOL

t

XOH

t

XI

t

XIR

t

XIS

Parameter

Shift Frequency

Read Cycle Time

Access Time

Read Recovery Time

Read Pulse Width

(3)

Read Pulse Low to Data Bus at Low Z

(4)

Write Pulse High to Data Bus at Low Z

(4, 5)

Data Valid from Read Pulse High

Read Pulse High to Data Bus at High Z

(4)

Write Cycle Time

Write Pulse Width

(3)

Write Recovery Time

Data Set-up Time

Data Hold Time

Reset Cycle Time

Reset Pulse Width

(3)

Reset Set-up Time

(4)

Reset Recovery Time

Retransmit Cycle Time

Retransmit Pulse Width

(3)

(4)

Com'l & Mil.

7200L50

7201LA50

7202LA50

Max.

15

—

50

—

30

—

65

45

—

45

65

—

50

—

65

—

15

50

10

15

5

—

65

50

15

30

5

65

50

15

65

50

15

—

50

—

50

—

50

10

15

7200L65

7201LA65

7202LA65

Min.

—

80

—

15

65

10

15

5

—

80

65

15

30

10

80

65

15

80

65

15

—

65

—

65

—

65

10

15

Max.

12.5

—

65

—

30

—

80

60

—

60

80

—

65

—

Military

(2)

7200L80

7201LA80

7202LA80

Min.

—

100

—

20

80

10

20

5

—

100

80

20

40

10

100

80

20

100

80

20

—

80

—

80

—

80

10

15

Max.

10

—

80

—

30

—

100

60

—

60

100

—

80

—

7200L120

7201LA120

7202LA120

Min.

—

140

—

20

120

10

20

5

—

140

120

20

40

10

140

120

20

140

120

20

—

120

—

120

—

120

10

15

Max.

7

—

120

—

35

—

140

60

—

60

140

—

120

—

Unit

MHz

ns

2679 tbl 07

Min.

—

50

—

10

40

5

10

5

—

50

40

10

20

0

50

40

10

50

40

10

—

40

—

40

—

40

10

Max. Min.

20

—

40

—

25

—

50

30

35

—

35

50

—

40

—

Retransmit Set-up Time

Retransmit Recovery Time

Reset to Empty Flag Low

Retransmit Low to Flags Valid

Read Low to Empty Flag Low

Read High to Full Flag High

Read Pulse Width after

EF

High

Write High to Empty Flag High

Write Low to Full Flag Low

Write Low to Half-Full Flag Low

Read High to Half-Full Flag High

Write Pulse Width after

FF

High

Read/Write to

XO

Low

Read/Write to

XO

High

t

HFH,FFH

Reset to Half-Full and Full Flag High

XI

Pulse Width

XI

Recovery Time

XI

Set-up Time

(3)

NOTES:

1. Timings referenced as in AC Test Conditions

2. Speed grades 65, 80 and 120 not available in the CERPACK

3. Pulse widths less than minimum value are not allowed.

4. Values guaranteed by design, not currently tested.

5. Only applies to read data flow-through mode.

5.03

5

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	QFJ
包装说明	QCCJ,
针数	32
Reach Compliance Code	compliant
ECCN代码	EAR99
最长访问时间	40 ns
周期时间	50 ns
JESD-30 代码	R-PQCC-J32
JESD-609代码	e0
长度	13.97 mm
内存密度	4608 bit
内存宽度	9
功能数量	1
端子数量	32
字数	512 words
字数代码	512
工作模式	ASYNCHRONOUS
最高工作温度	125 °C
最低工作温度	-55 °C
组织	512X9
可输出	NO
封装主体材料	PLASTIC/EPOXY
封装代码	QCCJ
封装形状	RECTANGULAR
封装形式	CHIP CARRIER
并行/串行	PARALLEL
峰值回流温度（摄氏度）	225
认证状态	Not Qualified
座面最大高度	3.55 mm
最大供电电压 (Vsup)	5.5 V
最小供电电压 (Vsup)	4.5 V
标称供电电压 (Vsup)	5 V
表面贴装	YES
技术	CMOS
温度等级	MILITARY
端子面层	TIN LEAD
端子形式	J BEND
端子节距	1.27 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	30
宽度	11.43 mm

IDT7201LA40JB

IDT7201LA40JB概述

IDT7201LA40JB规格参数

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