IDT74FCT162240AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT
BUFFER/LINE DRIVER
IDT74FCT162240AT/CT
FEATURES:
•
•
•
•
•
•
•
•
•
•
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical t
SK
(o) (Output Skew) < 250ps
Low input and output leakage
≤
1µA (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 5V ±10%
Balanced Output Drivers: ±24mA
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at V
CC
= 5V,
T
A
= 25°C
Available in SSOP and TSSOP packages
DESCRIPTION:
The FCT162240T 16-bit buffer/line driver is built using advanced dual metal
CMOS technology. These high-speed, low-power devices offer bus/backplane
interface capability with improved packing density. The flow-through organiza-
tion of signal pins simplifies layout. The three-state controls are designed to
operate these devices in a Quad-Nibble, Dual-Byte or single 16-bit word mode.
All inputs are designed with hysteresis for improved noise margin.
The FCT162240T have balanced output drive with current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall
times–reducing the need for external series terminating resistors. The
FCT162240T is a plug-in replacement for FCT16240T and 74ABT16240 for
on-board interface applications.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
Y
1
3
OE
1
A
1
1
A
2
3
A
1
3
A
2
3
Y
1
3
Y
2
1
Y
2
1
A
3
1
A
4
1
Y
3
3
A
3
3
Y
3
3
Y
4
1
Y
4
3
A
4
2
OE
2
Y
1
4
OE
2
A
1
2
A
2
2
A
3
4
A
1
4
A
2
4
A
3
4
Y
1
4
Y
2
4
Y
3
2
Y
2
2
Y
3
2
Y
4
2
A
4
4
A
4
4
Y
4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2002 Integrated Device Technology, Inc.
APRIL 2002
DSC-5464/6
IDT74FCT162240AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
O
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP/ TSSOP
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
O
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
Storage Temperature
DC Output Current
E
1
Y
1
1
Y
2
E
1
A
1
1
A
2
GN
D
1
Y
3
1
Y
4
V
CC
2
Y
1
2
Y
2
GN
D
1
A
3
1
A
4
V
CC
2
A
1
2
A
2
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals terminals for FCT162XXX.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
GN
D
2
Y
GN
D
2
A
3
2
A
4
3
A
1
3
A
2
GN
D
3
Y
3
3
Y
4
V
CC
4
Y
1
4
Y
2
3
2
Y
4
3
Y
1
3
Y
2
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
xOE
xA x
xY x
Data Inputs
3-State Outputs
Description
3-State Output Enable Inputs (Active LOW)
GN
D
3
A
3
3
A
4
V
CC
4
A
1
4
A
2
FUNCTION TABLE
(1)
Inputs
xOE
L
L
H
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
Outputs
xAx
L
H
X
xYx
H
L
Z
GN
D
4
Y
3
4
Y
4
4
O
GN
D
4
A
3
4
A
4
3
O
E
E
2
IDT74FCT162240AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current (Input pins)
(5)
Input HIGH Current (I/O pins)
(5)
I
IL
Input LOW Current (Input pins)
(5)
Input LOW Current (I/O pins)
(5)
I
OZH
I
OZL
V
IK
I
OS
V
H
I
CCL
I
CCH
I
CCZ
High Impedance Output Current
(3-State Output pins)
(5)
Clamp Diode Voltage
Short Circuit Current
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
—
V
CC
= Max.
V
O
= 2.7V
V
O
= 0.5V
V
I
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
I
= V
CC
Min.
2
—
—
—
—
—
—
—
—
–80
—
—
Typ.
(2)
—
—
—
—
—
—
—
—
–0.7
–140
100
5
Max.
—
0.8
±1
±1
±1
±1
±1
±1
–1.2
–250
—
500
V
mA
mV
µA
µA
Unit
V
V
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
I
ODL
I
ODH
V
OH
V
OL
Parameter
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
Test Conditions
(1)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 5V
,
V
IN =
V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min
I
OH
= –24mA
V
IN
= V
IH
or V
IL
V
CC
= Min
I
OH
= 24mA
V
IN
= V
IH
or V
IL
Min.
60
–60
2.4
—
Typ.
(2)
115
–115
3.3
0.3
Max.
200
–200
—
0.55
Unit
mA
mA
V
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. This test limit for this parameter is ±5µA at T
A
= –55°C.
3
IDT74FCT162240AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
xOE = GND
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
xOE = GND
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
xOE = GND
Sixteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
60
Max.
1.5
100
Unit
mA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
0.6
1.5
mA
—
0.9
2.3
—
2.4
4.5
(5)
—
6.4
16.5
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL
, I
CCH
and I
CCZ
)
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
fi = Input Frequency
Ni = Number of Inputs at fi
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK(o)
Parameter
Propagation Delay
xAx to xYx
Output Enable Time
Output Disable Time
Output Skew
(3)
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
FCT162240AT
Min.
(2)
Max.
1.5
4.8
1.5
1.5
—
6.2
5.6
0.5
FCT162240CT
Min.
(2)
Max.
1.5
3.4
1.5
1.5
—
4.4
4.1
0.5
Unit
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4
IDT74FCT162240AT/CT
FAST CMOS 16-BIT BUFFER/LINE DRIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V
CC
500Ω
V
IN
Pulse
Generator
R
T
D.U.T.
50pF
C
L
500Ω
V
OUT
SWITCH POSITION
Test
Switch
Closed
Open
Open Drain
Disable Low
Enable Low
All Other Tests
7.0V
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
Test Circuits for All Outputs
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
t
SU
t
H
t
REM
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
t
SU
t
H
Pulse Width
Set-Up, Hold, and Release Times
ENABLE
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
1.5V
0V
0V
3.5V
1.5V
t
PHZ
0.3V
V
OH
t
PLZ
0.3V
DISABLE
3V
1.5V
0V
3.5V
V
OL
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
5
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