AMD Geode™ Solutions
Integrated Processors, Companion
Devices, and System Platforms
September 2004
NOTICE
Advanced Micro Devices, Inc. (“AMD”) has purchased the Information Appliance business unit of
National Semiconductor Corporation (“National”), which consisted primarily of the Geode™ family of
microprocessor products and related support products (GX1/CS5530A, GX/CS5535, SC1100,
SC1200, SC1201, SC2200, SC3200, XpressROM and XpressLoader software, collectively, the “IA
Products”). This business unit is now being operated by AMD’s PCS Division.
During a transitional period, AMD will continue to use and distribute IA Product technical and mar-
keting documents originally produced by National in hard copy, pdf, html or other electronic format.
Notwithstanding the appearance in this document of the National trade names, National trademarks,
and National copyrights or other proprietary notices, AMD is the seller of the IA Products described
in this document, the owner of the content contained in this document, and the source/publisher of
this document.
Geode™ CS5530 I/O Companion Multi-Function South Bridge
April 2000
Geode™ CS5530 I/O Companion
Multi-Function South Bridge
General Description
The CS5530 I/O companion is designed to work in con-
junction with the GXLV and GXm series processors; all
members of the National Semiconductor
®
Geode™ family
of products. Together the Geode processor and CS5530
provide a system-level solution well suited for the high
performance needs of a host of devices such as digital
set-top boxes and thin client devices. Due to the low
power consumption of a GXLV processor, this solution
satisfies the needs of battery powered devices such as
National’s WebPAD™ system, a Geode GXLV proces-
sor/CS5530 based design. Also, thermal design is eased
allowing for fanless system design.
The CS5530 I/O companion is a PCI-to-ISA bridge (South
Bridge), ACPI-compliant chipset that provides AT/ISA
style functionality. To those familiar with PC architecture
this enables a quicker understanding of the CS5530’s
architecture. The device contains state-of-the-art power
management that enables systems, especially battery
powered systems, to significantly reduce power consump-
tion.
Audio is supported through PCI bus master engines which
connect to an AC97 compatible codec such as the
National Semiconductor LM4548. If industry standard
audio is required, a combination of hardware and software
called Virtual System Architecture
®
(VSA™) technology is
provided.
The GXLV processor’s graphics/video output is connected
to the CS5530. The CS5530 graphics/video support
includes a PLL that generates the DOT clock for the GXLV
processor (where the graphics controller is located), video
acceleration hardware, gamma RAM plus three DACs for
RGB output to CRT, and digital RGB that can be directly
connected to TFT panels or NTSC/PAL encoders. The
digital RGB output can also be connected to the National
Semiconductor CS9210 Graphics Companion (a DSTN
Controller) for DSTN panel support. The CS9210 is also a
member of the Geode product family.
Geode™ CS5530 Internal Block Diagram
PCI Bus
USB
PCI to USB Macro
GPIOs
GPCS
Pwr Mgmt, Traps,
Events, and Timers
PCI to X-Bus / X-Bus to PCI Bridge
CS5530 Support
PCI Configuration
Registers
Active Decode
Address Mapper
X-Bus Arbiter
X-Bus
Graphics
and Video
from CPU
Display Interface
MPEG, DOT Clock
CSC and SCL
RGB/FP Interface
AT Compatibility Logic
Audio/Codec/MPU
Interface
Display
Geode™ CS9210
Graphics Companion
ISA Bus Interface
AT Ports, ISA Megacells
Ultra DMA/33
IDE
Interface
AC97 Codec
(e.g., LM4548)
Joystick
Joystick / Game Port
ISA Bus
PC97317 SIO
IDE
National Semiconductor and Virtual System Architecture are registered trademarks of National Semiconductor Corporation.
Geode, VSA, and WebPAD are trademarks of National Semiconductor Corporation.
For a complete listing of National Semiconductor trademarks, please visit www.national.com/trademarks.
© 2000 National Semiconductor Corporation
www.national.com
Geode™ CS5530
Designed for use with the GXLV and GXm Geode
series processors
352-Terminal Tape Ball Grid Array (TBGA) package
3.3V or 5.0V PCI bus compatible
5.0V tolerant I/O interfaces
3.3V core
PCI-to-ISA Bridge
PCI 2.1 compliant
Supports PCI initiator-to-ISA and ISA master-to-PCI
cycle translations
PCI master for audio I/O and IDE controllers
Subtractive agent for unclaimed transactions
PCI-to-ISA interrupt mapper/translator
AT Compatibility
8254-equivalent timer
Two 8237-equivalent DMA controllers
Boot ROM and keyboard chip select
Extended ROM to 16 MB
Bus Mastering IDE Controllers
Two controllers with support for up to four IDE devices
Independent timing for master and slave devices for
both channels
PCI bus master burst reads and writes
Ultra DMA/33 (ATA-4) support
Multiword DMA support
Programmed I/O (PIO) Modes 0-4 support
www.national.com
2
Two 8259A-equivalent interrupt controllers
General Features
Features
Two bus mastering IDE controllers are included for sup-
port of up to four ATA-compliant devices. A two-port Uni-
versal Serial Bus (USB) provides high speed, Plug & Play
expansion for a variety of consumer peripheral devices
such as a keyboard, mouse, printer, and digital cameras.
If additional functions are required, such as real-time
clock, floppy disk, PS2 keyboard, and PS2 mouse, a
SuperI/O (e.g., National PC97317) can be easily con-
nected to the CS5530.
Power Management
Intelligent system controller supports multiple power
management standards:
— Full ACPI and Legacy (APM) support
— Directly manages all GXLV and GXm processor
power states (including automatic Suspend modula-
tion for optimal performance/thermal balancing)
I/O traps and idle timers for peripheral power
management
Up to eight GPIOs for system control:
— All eight are configurable as external wakeup events
Dedicated inputs for keyboard and mouse wakeup
events
XpressAUDIO
Provides "back-end" hardware support via six buffered
PCI bus masters
AC97 codec interface:
— Specification Revision 1.3, 2.0, and 2.1 compliant
interface. Note that the codec (e.g., LM4548) must
have SRC (sample rate conversion) support
Display Subsystem Extensions
Complements the GXLV and GXm processor’s
graphics and video capabilities:
— Three independent line buffers for accelerating
video data streams
— Handles asynchronous video and graphics data
streams concurrently from the processor
— YUV to RGB conversion hardware
— Arbitrary X & Y interpolative scaling
— Color keying for graphics/video overlay
VDACs / Display interface:
— Three integrated DACs
— Gamma RAM:
– Provides gamma correction for graphics data
streams
– Provides brightness/contrast correction for video
data streams
— Integrated DOT clock generator
— Digital RGB interface drives TFT panels or standard
NTSC/PAL encoders
Universal Serial Bus
Two independent USB interfaces:
— Open Host Controller Interface (OpenHCI)
specification compliant
— Second generation proven core design
Revision 4.1
Geode™ CS5530
Table of Contents
1.0
Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
PCI BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AT COMPATIBILITY LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.1
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.2
Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3.3
Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
IDE CONTROLLERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5.1
GPIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
XPRESSAUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6.1
AC97 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.6.2
VSA Technology Support Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DISPLAY SUBSYSTEM EXTENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CLOCK GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
UNIVERSAL SERIAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
PROCESSOR SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4
1.5
1.6
1.7
1.8
1.9
1.10
2.0
Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Reset Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7
IDE Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8
USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.9
Game Port and General Purpose I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.10 Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.11 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.12 DCLK PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.13 Power, Ground, and Reserved . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.14 Internal Test and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
22
22
22
23
24
27
30
31
32
32
33
34
38
39
39
3.0
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1
PROCESSOR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.1.1
Display Subsystem Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1.2
PSERIAL Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1.2.1
Video Retrace Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2
PCI BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
PCI Initiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
PCI Target . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Special Bus Cycles–Shutdown/Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4
PCI Bus Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.5
PCI Interrupt Routing Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.6
Delayed Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
45
46
47
47
48
48
Revision 4.1
3
www.national.com
Geode™ CS5530
Table of Contents
(Continued)
3.3
RESETS AND CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
ISA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
DOT Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3.1
49
49
49
50
DCLK Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.4
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4.1
APM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4.2
CPU Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.2.1
3.4.2.2
3.4.2.3
Suspend Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3 Volt Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Save-To-Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Device Idle Timers and Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACPI Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Purpose I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management SMI Status Reporting Registers . . . . . . . . . . . . . . . . . . . . . .
Device Power Management Register Programming Summary . . . . . . . . . . . . . . .
60
70
72
73
75
82
3.4.3
Peripheral Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
3.4.3.1
3.4.3.2
3.4.3.3
3.4.3.4
3.4.3.5
3.4.3.6
3.5
PC/AT COMPATIBILITY LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5.1
ISA Subtractive Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5.2
ISA Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.5.2.1
3.5.2.2
3.5.2.3
3.5.2.4
3.5.2.5
Delayed PCI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Limited ISA and ISA Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISA Bus Data Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Recovery Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISA DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
86
87
89
89
90
3.5.3
3.5.4
ROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Megacells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.5.4.1
3.5.4.2
3.5.4.3
3.5.4.4
Direct Memory Access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Compatible Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
94
95
98
3.5.5
I/O Ports 092h and 061h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.5.5.1
3.5.5.2
3.5.5.3
I/O Port 092h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
I/O Port 061h System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SMI Generation for NMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Fast Keyboard Gate Address 20 and CPU Reset . . . . . . . . . . . . . . . . . . . . . . . . 103
3.5.6
Keyboard Interface Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.5.6.1
3.6
3.5.7
External Real-Time Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDE CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
IDE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2
IDE Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2.1
3.6.2.2
3.6.2.3
104
105
105
106
PIO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Bus Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Ultra DMA/33 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
3.7
XPRESSAUDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.7.1
Subsystem Data Transport Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.7.1.1
3.7.1.2
3.7.1.3
3.7.1.4
3.7.1.5
Audio Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Physical Region Descriptor Table Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Physical Region Descriptor Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
AC97 Codec Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
VSA Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Audio SMI Related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
IRQ Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4
Revision 4.1
3.7.2
VSA Technology Support Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.7.2.1
3.7.2.2
3.7.2.3
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