Freescale Semiconductor
Data Sheet
Document Number: MSC8144
Rev. 16, 5/2010
MSC8144
FC-PBGA–783
29 mm
×
29 mm
Quad Core Digital Signal
Processor
• Four StarCore
®
SC3400 DSP subsystems, each with an SC3400
DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
memory management unit (MMU), extended programmable
interrupt controller (EPIC), two general-purpose 32-bit timers,
debug and profiling support, and low-power Wait and Stop
processing modes.
• Chip-level arbitration and system (CLASS) that provides full
fabric non-blocking arbitration between the processing elements
and other initiators and the M2 memory, DDR SRAM controller,
device configuration control and status registers, and other
targets.
• 128 Kbyte L2 shared instruction cache.
• 512 Kbyte M2 memory for critical data and temporary data
buffering.
• 10 Mbyte 128-bit wide M3 memory.
• 96 Kbyte boot ROM.
• Three input clocks (shared, global, and differential).
• Four PLLs (system, core, global, and serial RapidIO).
• DDR controller with up to a 200 MHz clock (400 MHz data rate),
16/32 bit data bus, supporting up to 1 Gbyte in up to two banks
and support for DDR1 and DDR2.
• DMA controller with 16 bidirectional channels with up to 1024
buffer descriptors, and programmable priority, buffer, and
multiplexing configuration.
• Up to eight independent TDM modules with programmable word
size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion,
up to 128 Mbps data rate for all channels, with glueless interface
to E1 or T1 framers, and can interface with H-MVIP/H.110
devices, TSI, and codecs such as AC-97.
• QUICC Engine™ technology subsystem with dual RISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
RAM, supporting three communication controllers with one ATM
and two Gigabit Ethernet interfaces, to offload scheduling tasks
from the DSP cores.
– The two Ethernet controllers support 10/100/1000 Mbps
operations via MII/RMII/SMII/RGMII/SGMII and the SGMII
protocol using a 4-pin SerDes interface at 1000 Mbps data rate
only.
– The ATM controller supports UTOPIA level II 8/16 bits at
25/50 MHz in UTOPIA/POS mode with adaptation layer
support AAL0, AAL2, and AAL5.
PCI designed to comply with the PCI specification revision 2.2 at
33 MHz or 66 MHz with access to all PCI address spaces.
Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2
of the RapidIO trade association, and supports read, write,
messages, doorbells, and maintenance accesses in inbound mode,
and messages and doorbells in outbound mode.
I/O interrupt concentrator consolidates all chip maskable interrupt
and non-maskable interrupt sources and routes them to
INT_OUT, NMI_OUT, and the cores.
UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
Serial peripheral interface (SPI).
Four timer modules, each with four configurable16-bit timers.
Four software watchdog timer (SWT) modules.
Up to 32 general-purpose input/output (GPIO) ports, 16 of which
can be configured as maskable interrupt inputs.
I
2
C interface that allows booting from EEPROM devices.
Eight programmable hardware semaphores.
Thirty two virtual maskable interrupts and one virtual NMI that
can be generated by a simple write access.
Optional booting via serial RapidIO port, PCI, I
2
C, SPI, or
Ethernet interfaces.
•
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Note:
This document supports mask set M31H.
© 2007–2010 Freescale Semiconductor, Inc.
Table of Contents
1
2
Pin Assignments and Reset States. . . . . . . . . . . . . . . . . . . . . .4
1.1 FC-PBGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27
2.3 Default Output Driver Characteristics . . . . . . . . . . . . . .28
2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .29
2.6 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .64
3.1 Start-up Sequencing Recommendations . . . . . . . . . . .64
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .66
3.3 Clock and Timing Signal Board Layout Considerations 67
3.4 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .67
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Figure 12.Transmitter Output Compliance Mask . . . . . . . . . . . . . .
Figure 13.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . .
Figure 14.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . .
Figure 15.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 16.PCI Input AC Timing Measurement Conditions . . . . . . .
Figure 17.PCI Output AC Timing Measurement Condition . . . . . .
Figure 18.TDM Inputs Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 20.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 21.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23.Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 24.MII Management Interface Timing . . . . . . . . . . . . . . . . .
Figure 25.MII Transmit AC Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 26.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 27.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 28.RMII Transmit and Receive AC Timing . . . . . . . . . . . . .
Figure 29.AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 30.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . .
Figure 31.RGMII AC Timing and Multiplexing . . . . . . . . . . . . . . . .
Figure 32.ATM/UTOPIA/POS AC Test Load . . . . . . . . . . . . . . . . .
Figure 33.ATM/UTOPIAPOS AC Timing (External Clock) . . . . . . .
Figure 34.SPI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 35.SPI AC Timing in Slave Mode (External Clock). . . . . . .
Figure 36.SPI AC Timing in Master Mode (Internal Clock) . . . . . .
Figure 37.Asynchronous Signal Timing . . . . . . . . . . . . . . . . . . . . .
Figure 38.Test Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 39.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . .
Figure 40.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . .
Figure 41.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 42.V
DDM3
, V
DDM3IO
and V
25M3
Power-on Sequence . . . . .
Figure 44.MSC8144 Mechanical Information, 783-ball FC-PBGA
Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
48
49
51
51
51
52
53
53
53
54
55
55
56
56
57
57
58
59
60
60
61
61
62
62
63
63
64
64
65
77
3
4
5
6
7
List of Figures
MSC8144 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
StarCore SC3400 DSP Core Subsystem Block Diagram 3
MSC8144 FC-PBGA Package, Top View . . . . . . . . . . . . 4
MSC8144 FC-PBGA Package, Bottom View . . . . . . . . . 5
SerDes Reference Clocks Input Stage . . . . . . . . . . . . . 31
Start-Up Sequence with V
DD
Raised Before V
DDIO
with
CLKIN Started with V
DDIO
. . . . . . . . . . . . . . . . . . . . . . . 35
Figure 7. Timing for a Reset Configuration Write . . . . . . . . . . . . . 38
Figure 8. Timing for t
DDKHMH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 9. DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41
Figure 10.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 11.Differential V
PP
of Transmitter or Receiver . . . . . . . . . . 42
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
2
Freescale Semiconductor
DDR Interface 16/32-bit at 400 MHz data rate
512 Kbytes
M2
Memory
10 Mbytes
M3
Memory
128-bit at
400 MHz
CLASS
QUICC Engine
Subsystem
8 TDMs
Four DSP
Subsystems
128 Kbyte
L2
ICache
Dual RISC
Processors
Ethernet
Ethernet
ATM
SPI
DMA
DDR
Controller
I/O-Interrupt
Concentrator
UART
Clocks
Timers
Reset
Serial RapidIO
Subsystem
PCI
RMU
SRIO
Semaphores
Virtual
Interrupts
Boot ROM
I
2
C
Other
Modules
JTAG
Eight TDMs
256-Channels each
10/100/1000 Mbps
10/100/1000 Mbps
SPI
PCI 32-bit
33/66 MHz
1x/4x
Note: The arrow direction indicates master or slave.
16-bit/8-bit
UTOPIA
Figure 1. MSC8144 Block Diagram
Two Internal Buses
(128 bits wide each)
Interrupts
Bus Interface
IQBus
TWB
DQBus
EPIC
Timer
Task
Protection
Debug Support
OCE30 DPU
Instruction
Cache
Write-
Through
Buffer
Data
Cache
Write-
Back
Buffer
Address
Translation
MMU
(WTB)
(WBB)
SC3400
Core
P-bus
Xa-bus
Xb-bus
Figure 2. StarCore SC3400 DSP
Core
Subsystem Block Diagram
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
3
Pin Assignments and Reset States
1
Pin Assignments and Reset States
This section includes diagrams of the MSC8144 package ball grid array layouts and tables showing how the pinouts are
allocated for the package.
1.1
FC-PBGA Ball Layout Diagrams
Top and bottom views of the FC-PBGA package are shown in
Figure 3
and
Figure 4
with their ball location index numbers.
Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MSC8144
Figure 3. MSC8144 FC-PBGA Package, Top View
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
4
Freescale Semiconductor
Bottom View
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28
Figure 4. MSC8144 FC-PBGA Package, Bottom View
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
5
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