IDT74ALVCH16282
3.3V CMOS 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT TO
36-BIT REGISTERED BUS
EXCHANGER WITH 3-STATE
OUTPUTS AND BUS-HOLD
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 1.65V ± 3.6V
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-Rail output swing for increased noise margin
• Available in TVSOP package
IDT74ALVCH16282
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONAL BLOCK DIAGRAM
CLK
39
40
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2000 Integrated Device Technology, Inc.
R
FO E
C N
R O
O
N M T
EW M
EN
D
ES DE
IG D
N
S
SEL
OE
42
This 18-bit to 36-bit registered bus exchanger is manufactured using
advanced dual metal CMOS technology. This device is intended for use in
applications in which data must be transferred from a narrow high-speed bus
to a wide lower-frequency bus.
The ALVCH16282 provides synchronous data exchange between the
two ports. Data is stored in the internal registers on the low-to-high transition
of the clock (CLK) input. For data transfer in the B-to-A direction, the select
(SEL) input selects 1B or 2B data for the A outputs. For data transfer in the
A-to-B direction, a two-stage pipeline is provided in the 1B path, with a single
storage register in the 2B path. Data flow is controlled by the active-low output
enable (OE) and the DIR input. The DIR control pin is registered to
synchronize the bus direction changes with the clock.
The ALVCH16282 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16282 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
CE
C1
D IR
41
1D
1 of 18 Channels
25
1
B
1
C1
A
1
27
1D
1
CE
C1
0
1D
24
2
B
1
C1
CE
C1
1D
1D
CE
C1
1D
JULY 2000
DSC-4749/1
IDT74ALVCH16282
3.3V CMOS 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
V
CC
GND
2
B
9
1
B
9
2
B
8
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
(2)
Terminal Voltage with Respect to GND
–0.5 to +4.6
–0.5 to V
CC
+0.5
–65 to +150
–50 to +50
±50
–50
±100
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
CC
GND
1
B
10
2
B
10
1
B
11
Unit
V
V
°C
mA
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
V
TERM
(3)
Terminal Voltage with Respect to GND
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
I
> V
CC
Continuous Clamp Current, V
O
< 0
Continuous Current through each
V
CC
or GND
GND
1
B
8
2
B
7
1
B
7
GND
2
B
11
1
B
12
2
B
12
V
CC
2
B
6
1
B
6
2
B
5
1
B
5
V
CC
1
B
13
2
B
13
1
B
14
2
B
14
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminals.
3. All terminals except V
CC
.
GND
2
B
4
1
B
4
2
B
3
1
B
3
GND
1
B
15
2
B
15
1
B
16
2
B
16
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
5
7
7
Max.
—
—
—
Unit
pF
pF
pF
V
CC
GND
2
B
2
1
B
2
2
B
1
1
B
1
V
CC
GND
1
B
17
2
B
17
1
B
18
2
B
18
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
OE
CLK
SEL
Ax
xBx
DIR
Description
3-State Output Enable Input (Active LOW)
Register Input Clock
Select Input
Data Inputs or 3-State Outputs
(1)
Data Inputs or 3-State Outputs
(1)
Direction Control Input
V
CC
A
1
A
2
A
3
GND
A
4
A
5
A
6
V
CC
A
7
A
8
A
9
GND
CLK
SEL
V
CC
A
18
A
17
A
16
GND
A
15
A
14
A
13
V
CC
A
12
A
11
A
10
GND
OE
DIR
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
TVSOP
TOP VIEW
2
IDT74ALVCH16282
3.3V CMOS 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLES
(1)
A-TO-B STORAGE (OE = L AND DIR = H)
Inputs
SEL
H
L
L
CLK
X
↑
↑
Ax
X
L
H
1
Bx
1
B
0(2)
OUTPUT ENABLE
Inputs
2
Bx
2
B
0(2)
Outputs
CLK
↑
↑
↑
X
OE
H
L
L
L
Outputs
DIR
X
H
L
X
Ax
Z
Z
Active
A
0(2)
1
Bx,
2
Bx
SEL
X
L
L
H
Z
Active
Z
1
B
0(2)
,
2
B
0(2)
L
(3)
H
(3)
L
H
B-TO-A STORAGE (OE = L AND DIR = L)
Inputs
SEL
H
H
L
L
CLK
↑
↑
↑
↑
1
Bx
2
Bx
Output
Ax
L
(4)
H
(4)
L
H
X
X
L
H
L
H
X
X
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑
= LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
3. Two CLK edges are needed to propagate data.
4. Two CLK edges are needed to propagate data. The data is loaded in the first register when
SEL
is LOW and propagates to the second register when
SEL
is HIGH.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
Parameter
V
CC
= 1.65V to 1.95V
Input HIGH Voltage Level
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 1.65V to 1.95V
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Input LOW Voltage Level
Input HIGH Current
Input LOW Current
High Impedance Output Current
(excluding bus-hold pins)
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= V
CC
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
Min.
0.65 x V
CC
1.7
2
—
—
—
—
—
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
—
—
—
—
100
0.1
Max.
—
—
—
0.35 x V
CC
0.7
0.8
±5
±5
±10
±10
—
40
mV
µA
µA
µA
µA
V
V
Unit
Quiescent Power Supply Current
Variation
—
—
750
µA
NOTE:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
3
IDT74ALVCH16282
3.3V CMOS 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
I
BHH
I
BHL
I
BHH
I
BHL
I
BHHO
I
BHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
Parameter
(1)
Bus-Hold Input Sustain Current
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
V
CC
= 3V
V
CC
= 2.3V
V
CC
= 3.6V
Test Conditions
V
I
= 2V
V
I
= 0.8V
V
I
= 1.7V
V
I
= 0.7V
V
I
= 0 to 3.6V
Min.
– 75
75
– 45
45
—
Typ.
(2)
—
—
—
—
—
Max.
—
—
—
—
±500
Unit
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 1.65V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 1.65V to 3.6V
V
CC
= 1.65V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
I
OH
= – 24mA
I
OL
= 4mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 12mA
I
OL
= 12mA
I
OL
= 24mA
Test Conditions
(1)
V
CC
= 1.65V to 3.6V
I
OH
= – 4mA
I
OH
= – 4mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 1.2
1.2
2
1.7
2.2
2.4
2
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.45
0.45
0.4
0.7
0.4
0.55
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
OPERATING CHARACTERISTICS, T
A
= 25°C
V
CC
= 2.5V ± 0.2V
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance Outputs enabled
Power Dissipation Capacitance Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
282
208
V
CC
= 3.3V ± 0.3V
Typical
310
228
Unit
pF
4
IDT74ALVCH16282
3.3V CMOS 18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.5V ± 0.2V
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
SU
t
SU
t
SU
t
SU
t
H
t
H
t
H
t
H
t
W
Propagation Delay
CLK to Ax
Propagation Delay
CLK to xBx
Output Enable Time
CLK to Ax
Output Enable Time
CLK to xBx
Output Disable Time
CLK to Ax
Output Disable Time
CLK to xBx
Output Enable Time
OE
to Ax
Output Enable Time
OE
to xBx
Output Disable Time
OE
to Ax
Output Disable Time
OE
to xBx
Set-up Time, Ax data before CLK↑
Set-up Time, xBx data before CLK↑
Set-up Time, DIR data before CLK↑
Set-up Time,
SEL
before CLK↑
Hold Time, Ax data after CLK↑
Hold Time, xBx data after
LE
Hold Time, DIR after CLK↑
Hold Time,
SEL
after CLK↑
Pulse Width, CLK HIGH or LOW
2.4
2.2
2.2
2
0.5
0.5
0.5
0.7
3.3
—
—
—
—
—
—
—
—
—
2.3
2.2
2.1
2
0.5
0.5
0.5
0.7
3.3
—
—
—
—
—
—
—
—
—
2
1.8
1.7
1.8
0.7
0.6
0.5
0.8
3.3
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.1
7.9
—
6.4
2.3
6.4
ns
1.5
7
—
5.6
1.8
5.7
ns
2.3
8.7
—
8.1
2.3
7.4
ns
1.3
6.9
—
6.3
1.2
5.7
ns
1.5
6.9
1.3
6.3
1.2
5.7
ns
1.5
6.9
1.3
6.3
1.2
5.7
ns
1.5
6.5
1.3
6.1
1.2
5.7
ns
1.5
6.5
1.3
6.1
1.2
5.7
ns
1.2
6.3
—
5.7
1.6
5.3
ns
Parameter
Min.
150
1
Max.
—
6.1
V
CC
= 2.7V
Min.
150
—
Max.
—
5.5
V
CC
= 3.3V ± 0.3V
Min.
150
1.4
Max.
—
5
Unit
MHz
ns
NOTE:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
5
能源基础设施
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
