Features
•
•
•
•
•
•
•
Superscalar (3 Instructions per Clock Peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On-chip Debug Support
Nap, Doze and Sleep Power Saving Modes
Device Offered in Cerquad, CBGA 255 and CI-CGA 255
Features Specific to CBGA 255 and CI-CGA 255
•
•
•
•
•
•
•
•
•
•
•
7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
P
D
Typically = 3.5W (266 MHz), Full Operating Conditions
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4-Gbytes Direct Addressing Range
Pipelined Single/Double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
f
INT
Max = 300 MHz
f
BUS
Max = 75 MHz
Compatible CMOS Input/TTL Output
PowerPC
®
603e
RISC
Microprocessor
Family
PID7t-603e
TSPC603R
Features Specific to Cerquad
•
5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)
•
P
D
Typically = 2.5W (200 MHz), Full Operating Conditions
Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a
low-power implementation of the Reduced Instruction Set Computer (RISC) micropro-
cessor PowerPC family. The 603R is pin-to-pin compatible with the PowerPC 603e
and 603P in a Cerquad package. The 603R implements 32-bit effective addresses,
integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
The 603R is a low-power 2.5/3.3V design and provides four software controllable
power-saving modes. This device is a superscalar processor capable of issuing and
retiring as many as three instructions per clock. Instructions can be executed in any
order for increased performance, but, the 603R makes completion appear sequential.
It integrates five execution units and is able to execute five instructions in parallel.
The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physi-
cally addressed caches for instructions and data, as well as on-chip instructions, and
data Memory Management Units (MMUs). The MMUs contain 64-entry, two-way
set-associative, data and instruction translation look aside buffers that provide support
for demand-paged virtual memory address translation and variable-sized block trans-
lation.
The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The inter-
face protocol allows multiple masters to compete for system resources through a
central external arbiter. The device supports single-beat and burst data transfers for
memory accesses, and supports memory-mapped I/Os.
The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full
interface compatibility with TTL devices. It also integrates in-system testability and
debugging features through JTAG boundary-scan capabilities.
Rev. 5410A–HIREL–10/04
Screening/Quality/
Packaging
This product is manufactured in full compliance with:
•
•
•
•
•
•
•
CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to Atmel standards
CBGA 255: Upscreenings based upon Atmel standards
Full Military Temperature Range (T
C
= -55°C, T
C
= +125°C)
Industrial Temperature Range
(T
C
= -40°C, T
C
= +110°C)
Cerquad: Commercial temperature ranges (
T
C
= 0°C,
T
C
= +70°C)
Internal/IO Power Supply = 2.5 ±5% // 3.3V ±5%
255-lead CBGA Package and 255-lead CBGA with SCI (CI-CGA) Package
G suffix
CBGA 255
Ceramic Ball Grid Array
GS suffix
CI-CGA 255
Ceramic Ball Grid Array
with Solder Column Interposer (SCI)
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier
Cavity up
CERQUAD 240
Block Diagram
Figure 1.
Block Diagram
Fetch
Unit
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
Unit
Gen
Re-
name
Load/
Store
Unit
FP
Re-
name
FP
Reg
File
Float
Unit
D MMU
16K Data Cache
I MMU
16K Inst. Cache
Bus Interface Unit
32b Address
System Bus
64b Data
2
TSPC603R
5410A–HIREL–10/04
TSPC603R
Overview
The 603R is a low-power implementation of the PowerPC microprocessor family of
Reduced Instruction Set Computing (RISC) microprocessors. The 603R implements the
32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses,
integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits.
For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer
data types, 64-bit addressing, and other features required to complete the 64-bit
architecture.
The 603R provides four software controllable power-saving modes. Three of the modes
(nap, doze, and sleep) are static in nature, and progressively reduce the amount of
power dissipated by the processor. The fourth is a dynamic power management mode
that causes the functional units in the 603R to automatically enter a low-power mode
when the functional units are idle without affecting operational performance, software
execution, or any external hardware.
The 603R is a superscalar processor capable of issuing and retiring as many as three
instructions per clock. Instructions can be executed in any order for increased perfor-
mance, but, the 603R makes completion appear sequential.
The 603e integrates five execution units:
•
•
•
•
•
an Integer Unit (IU)
a Floating-point Unit (FPU)
a Branch Processing Unit (BPU)
a Load/Store Unit (LSU)
a System Register Unit (SRU)
The ability to execute five instructions in parallel and the use of simple instructions with
rapid execution times yield high efficiency and throughput for 603R-based systems.
Most integer instructions execute in one clock cycle. The FPU is pipelined so a sin-
gle-precision multiply-add instruction can be issued every clock cycle.
The 603R provides independent on-chip, 16 Kbyte, four-way set-associative, physically
addressed caches for instructions and data, as well as on-chip instruction and data
Memory Management Units (MMUs). The MMUs contain 64-entry, two-way set-associa-
tive, Data and Instruction Translation Lookaside Buffers (DTLB and ITLB) that provide
support for demand-paged virtual memory address translation and variable-sized block
translation. The TLBs and caches use a Least Recently Used (LRU) replacement algo-
rithm. The 603R also supports block address translation through the use of two
independent Instruction and Data Block Address Translation (IBAT and DBAT) arrays of
four entries each. Effective addresses are compared simultaneously with all four entries
in the BAT array during block translation. In accordance with the PowerPC architecture,
if an effective address hits in both the TLB and BAT array, the BAT translation has
priority.
The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603R
interface protocol allows multiple masters to compete for system resources through a
central external arbiter. The 603R provides a three-state coherency protocol that sup-
ports the exclusive, modified, and invalid cache states. This protocol is a compatible
subset of the MESI (Modified/Exclusive/Shared/Invalid) four-state protocol and operates
coherently in systems that contain four-state caches. The 603R supports single-beat
and burst data transfers for memory accesses, and supports memory-mapped I/Os.
The 603R uses an advanced, 0.29 µm 5-metal-layer CMOS process technology and
maintains full interface compatibility with TTL devices.
3
5410A–HIREL–10/04
Signal Description
Figure 2, Tables 8 and 9 on page 19 describe the signals on the TSPC603R and indi-
cate signal functions. The test signals, TRST, TMS, TCK, TDI and TDO, comply with the
subset P-1149.1 of the IEEE testability bus standard.
The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for fac-
tory use only and must be pulled up to V
DD
for normal machine operations.
Figure 2.
Functional Signal Groups
BR
ADDRESS
ARBITRATION
BG
ABB
1
1
1
1
1
1
DBG
DBWO
DBB
DATA
ATTRIBUTION
ADDRESS
START
TS
1
64
8
DH[0-31], DL[0-31]
DP[0-7]
DPE
DBDIS
TA
DR TR Y
TEA
INT, SMI
MCP
CKSTP_IN, CKSTP_OUT
HRESET, SRESET
RSRV
QREQ, QACK
TBEN
TLBISYNC
PROCESSOR
STATUS
INTERRUPTS
CHECKSTOPS
RESET
DATA
TERMINATION
DATA
TRANSFER
A[0-31]
ADDRESS
BUS
AP[0-3]
APE
TT[0-4]
TBST
TSIZ[0-2]
GBL
TRANSFER
ATTRIBUTE
CI
WT
CSE[0-1]
TC[0-1]
32
4
1
5
1
3
1
1
1
2
2
603r
1
1
1
1
1
2
1
2
2
1
2
1
ADDRESS
TERMINATION
AACK
ARTRY
1
1
1
5
TRST, TCK, TMS, TDI, TD0
LSSD_MODE
L1_TSTCLK, L2_TSTCLK
VDD
OVDD
GND
AVDD
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
SYSCLK
CLOCKS
CLK_OUT
PLL_CFG[0-3]
POWER SUPPLY
INDICATOR
VOLTDETGND
1
1
4
20
1
19
40
1
3
POWER SUPPLY
4
TSPC603R
5410A–HIREL–10/04
TSPC603R
Detailed
Specifications
Applicable
Documents
This specification describes the specific requirements for the microprocessor
TSPC603R, in compliance with MIL-STD-883 class B or Atmel standard screening.
1. MIL-STD-883: Test methods and procedures for electronics
2. MIL-PRF-38535: General specifications for microcircuits
The microcircuits are in accordance with the applicable documents and as specified
herein.
Design and Construction
Terminal Connections
Depending on the package, the terminal connections are as shown in Table 5 on page
14, Table 7 on page 17, “Recommended Operating Conditions” on page 6, Figure 17 on
page 47, Figure 19 on page 49 and Figure 2 on page 4.
Lead material and finish shall be as specified in MIL-STD-1835. (See “Package
Mechanical Data” on page 46.)
Absolute maximum ratings are stress ratings only and functional operation at the maxi-
mum is not guaranteed. Stresses beyond those listed may affect device reliability or
cause permanent damage to the device.
Absolute Maximum Ratings for the 603R
(1)(2)(3)
Parameter
Core supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
Storage temperature range
Notes:
Symbol
V
DD
AV
DD
OV
DD
V
IN
T
STG
Min
-0.3
-0.3
-0.3
-0.3
-55
Max
2.75
2.75
3.6
5.5
+150
Unit
V
V
V
V
°C
Lead Material and Finish
Absolute Maximum
Ratings
1.
Caution:
The input voltage must not be greater than OV
DD
by more than 2.5V at any
time, including during power-on reset.
2.
Caution:
The OV
DD
voltage must not be greater than V
DD
/AV
DD
by more than 1.2V at
any time, including during power-on reset.
3.
Caution:
The V
DD
/AV
DD
voltage must not be greater than OV
DD
by more than 0.4V at
any time, including during power-on reset.
Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond
the absolute maximums listed may affect device reliability or cause permanent damage to the
device.
5
5410A–HIREL–10/04
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