3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
8,192 x 8,192
IDT72V73250
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
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8K x 8K non-blocking switching at 32.768Mb/s
16 serial input and output streams
Accepts single-bit single-data streams at 32.768Mb/s
Per-channel Variable Delay Mode for low-latency applications
Per-channel Constant Delay Mode for frame integrity applications
Automatic identification of ST-BUS
®
and GCI bus interfaces
Automatic frame offset delay measurement
Per-stream single data frame delay offset programming
Per-channel high-impedance output control
Direct microprocessor access to all internal memories
Memory block programming for quick setup
IEEE-1149.1 (JTAG) Test Port
3.3V Power Supply
Available in 144-pin (20mm x 20mm) Thin Quad Flatpack (TQFP)
and 144-pin (13mm x 13mm) Plastic Ball Grid Array (PBGA)
Operating Temperature Range -40°C to +85°C
°
°
DESCRIPTION:
The IDT72V73250 has a non-blocking switch capacity of 8,192 x 8,192
channels at 32.768Mb/s. With 16 inputs and 16 outputs, programmable per
stream control, and a variety of operating modes the IDT72V73250 is designed
for the TDM time slot interchange function in either voice or data applications.
Some of the main features of the IDT72V73250 are LOW power 3.3 Volt
operation, automatic ST-BUS
®
/GCI sensing, memory block programming,
simple microprocessor interface, JTAG Test Access Port (TAP) and per stream
programmable input offset delay, variable or constant throughput modes, output
enable and processor mode.
The IDT72V73250 is capable of switching up to 8,192 x 8,192 channels
without blocking. Designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data, the
device maintains frame integrity in data applications and minimizes throughput
delay for voice applications on a per-channel basis.
The 16 serial input streams (RX) of the IDT72V73250 are run at 32.768Mb/s
allowing 512 channels per 125μs frame. The data rates on the output streams
(TX) are identical to those on the input streams (RX).
FUNCTIONAL BLOCK DIAGRAM
V
CC
GND
R ESET
ODE
TX0
RX0
RX1
Data Memory
MUX
TX1
Receive
Serial Data
Streams
Internal
Registers
RX15
Connection
Memory
Transmit
Serial Data
Streams
TX7
TX8/OEI0
TX9/OEI1
TX15/OEI7
Timing Unit
Microprocessor Interface
JTAG Port
C32i
F32i
FE
DS
CS
R/W
A0-A14
D TA
D0-D15
TMS TDI TCK TDO
TR ST
5933 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
®
is a trademark of Mitel Corp.
JUNE 2004
DSC-5933/10
1
IDT72V73250 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A1 BALL PAD CORNER
A
C32i
R ESET
ODE
RX1
RX4
RX7
TX4
TX7
NC
(1)
NC
(1)
NC
(1)
NC
(1)
B
F32i
FE
TMS
RX0
TDI
RX2
RX3
RX5
RX6
TX0
TX1
TX3
TX2
TX6
TX5
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
C
NC
(1)
D
TDO
TCK
R/W
TR ST
A0
DS
V
CC
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
NC
(1)
VCC
NC
(1)
RX10
NC
(1)
RX9
NC
(1)
E
CS
GND
RX8
F
A1
A2
A3
V
CC
GND
GND
GND
GND
VCC
RX13
RX14
RX12
RX15
RX11
TX8/
OEI0
TX11/
OEI3
TX14/
OEI6
NC
(1)
NC
(1)
G
A6
A5
A4
V
CC
GND
GND
GND
GND
VCC
H
A9
A8
A12
A7
A11
V
CC
A10
GND
GND
V
CC
GND
GND
V
CC
V
CC
NC
(1)
TX9/
OEI1
TX12/
OEI4
NC
(1)
NC
(1)
TX10/
OEI2
TX13/
OEI5
TX15/
OEI7
NC
(1)
J
A13
V
CC
V
CC
K
NC
(1)
NC
(1)
A14
D11
D12
D8
D9
D10
D5
D2
D1
NC
(1)
NC
(1)
NC
(1)
NC
(1)
L
D15
D TA
D13
D6
D7
D3
D4
D0
M
D14
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
1
2
3
4
5
6
7
8
9
10
11
12
5933 drw02
NOTE:
1. NC = No Connect.
PBGA: 1mm pitch, 13mm x13mm (BB144-1, order code: BB)
TOP VIEW
2
IDT72V73250 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONTINUED)
GND
V
CC
NC
(1)
NC
(1)
NC
(1)
NC
(1)
GND
V
CC
NC
(1)
NC
(1)
NC
(1)
NC
(1)
GND
V
CC
TX7
TX6
TX5
TX4
GND
V
CC
TX3
TX2
TX1
TX0
GND
V
CC
RX7
RX6
RX5
RX4
RX3
RX2
RX1
RX0
ODE
R ESET
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
RX8
RX9
RX10
RX11
RX12
RX13
RX14
RX15
GND
V
CC
TX8/OEI0
TX9/OEI1
TX10/OEI2
TX11/OEI3
GND
V
CC
TX12/OEI4
TX13/OEI5
TX14/OEI6
TX15/OEI7
GND
V
CC
NC
(1)
NC
(1)
NC
(1)
NC
(1)
GND
V
CC
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
NC
(
1
)
NC
(
1
)
NC
(
1
)
NC
(
1
)
GND
NC
(
1
)
NC
(
1
)
NC
(
1
)
NC
(
1
)
NC
(
1
)
NC
(
1
)
NC
(
1
)
NC
(
1
)
NC
(
1
)
GND
V
CC
D0
D1
D2
D3
GND
VCC
D4
D5
D6
D7
GND
V
CC
D8
D9
D10
D11
GND
V
CC
D12
D13
·
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
5933 drw03
PIN 1
NOTE:
1. NC = No Connect.
GND
C32i
F32i
FE
NC
(1)
TMS
TDI
TDO
TCK
TRST
DS
CS
R/W
V
CC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
NC
(1)
NC
(1)
D TA
V
CC
GND
D15
D14
TQFP: 0.50mm pitch, 20mm x 20mm (DA144-1, order code: DA)
TOP VIEW
3
IDT72V73250 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
A0-14
C32i
CS
D0-15
DS
DTA
NAME
Address 0 to 14
Clock
Chip Select
Data Bus 0-15
Data Strobe
Data Transfer
Acknowledgment
Frame Evaluation
I/O
I
I
DESCRIPTION
These address lines access all internal memories.
Serial clock for shifting data in/out on the serial data stream. This input accepts a 32.768 MHz clock.
I This active LOW input is used by a microprocessor to activate the microprocessor port of IDT72V73250.
I/O These pins are the data bits of the microprocessor port.
I
O
This active LOW input works in conjunction with
CS
to enable the read and write operations and sets the
data bus lines (D0-D15).
Indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes
high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required
to hold a HIGH level when the pin is in high-impedance.
This input can be used to measure delay in the data path by comparing the frame pulse, F32i, with this input.
FE
I
F32i
GND
ODE
Frame Pulse
Ground
Output Drive Enable
I
This input accepts and automatically identifies frame synchronization signals formatted according to
ST-BUS
®
and GCI specifications.
Ground Rail
This is the output enable control for the TX serial outputs. When the ODE input is LOW and the Output Stand
By bit of the Control Register is LOW, all TX outputs are in a high-impedance state. If this input is HIGH, the TX
output drivers are enabled. However, each channel may still be put into a high-impedance state by using the
per-channel control bits in the Connection Memory.
This input puts the IDT72V73250 into a reset state that clears the device internal counters, registers and
brings TX0-15 and D0-D15 into a high-impedance state. The
RESET
pin must be held LOW for a minimum
of 20ns to properly reset the device.
This input controls the direction of the data bus lines (D0-D15) during a microprocessor access.
Serial data input stream. These streams have a data rate of 32.768 Mb/s.
Provides the clock to the JTAG test logic.
JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up
when not driven.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state
when JTAG scan is not enabled.
JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal
pull-up when not driven.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is
pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW,
to ensure that the IDT72V73250 is in the normal functional mode.
Serial data output stream. These streams have a data rate of 32.768 Mb/s.
When all 16 output streams are selected via Control Register, these pins are the output streams TX8 to TX15
and operate at 32.768Mb/s. When output enable function is selected, these pins reflect the active or high-
impedance status for the corresponding output stream Output Enable Indication 0-7.
+3.3 Volt Power Supply.
I
RESET
Device Reset
I
R/W
RX0-15
TCK
TDI
TDO
TMS
TRST
Read/Write
Data Stream
Input 0 to 15
Test Clock
Test Serial Data In
Test Serial Data Out
Test Mode Select
Test Reset
I
I
I
I
O
I
I
TX0-7
TX8-15/
OEI0-7
TX Output 0 to 7
(Three-State Outputs)
TX Output 8 to 15/
Output Enable
Indication0-7
(Three-State Outputs)
V
CC
O
O
V
CC
4
IDT72V73250 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 8,192 x 8,192
INDUSTRIAL TEMPERATURE RANGE
With two main operating modes, Processor Mode and Connection Mode, the
IDT72V73250 can easily switch data from incoming serial streams (Data
Memory) or from the controlling microprocessor via Connection Memory. As
control and status information is critical in data transmission, the Processor Mode
is especially useful when there are multiple devices sharing the input and output
streams.
With data coming from multiple sources and through different paths, data
entering the device is often delayed. To handle this problem, the IDT72V73250
has a Frame Evaluation feature to allow individual streams to be offset from the
frame pulse in half clock-cycle intervals up to +7.5 clock cycles.
The IDT72V73250 also provides a JTAG test access port, memory block
programming, a simple microprocessor interface and automatic ST-BUS
®
/GCI
sensing to shorten setup time, aid in debugging and ease use of the device
without sacrificing capabilities.
DESCRIPTION (CONTINUED)
SERIAL DATA INTERFACE TIMING
For a 32.768Mb/s serial data rate , the master clock frequency will be running
at 32.768 MHz resulting in a single-bit per clock. The IDT72V73250 provides
two different interface timing modes, ST-BUS
®
or GCI.
The IDT72V73250 automatically detects the presence of an input frame
pulse and identifies it as either ST-BUS
®
or GCI. In ST-BUS
®
Mode, data is
clocked out on the falling edge and is clocked in on the subsequent rising-edge.
See Figure 12 for timing. In GCI Mode, data is clocked out on the rising edge
and is clocked in on the subsequent falling edge. See Figure 13 for timing.
INPUT FRAME OFFSET SELECTION
Input frame offset selection allows the channel alignment of individual input
streams to be offset with respect to the output stream channel alignment. Although
all input data comes in at the same speed, delays can be caused by variable
path serial backplanes and variable path lengths which may be implemented
in large centralized and distributed switching systems. Because data is often
delayed, this feature is useful in compensating for the skew between input
streams.
Each input stream can have its own delay offset value by programming the
frame input offset registers (FOR, Table 8). The maximum allowable skew is +7.5
master clock (C32i) periods forward with a resolution of ½ clock period, see
Table 9. The output frame cannot be adjusted.
SERIAL INPUT FRAME ALIGNMENT EVALUATION
The IDT72V73250 provides the Frame Evaluation input to determine
different data input delays with respect to the frame pulse F32i. A measurement
cycle is started by setting the Start Frame Evaluation bit of the Control Register
LOW for at least one frame. When the Start Frame Evaluation bit in the Control
Register is changed from LOW to HIGH, the evaluation starts. Two frames later,
the Complete Frame Evaluation bit of the Frame Alignment Register changes
from LOW to HIGH to signal that a valid offset measurement is ready to be read
from bits 0 to 12 of the Frame Alignment Register. The Start Frame Evaluation
bit must be set to zero before a new measurement cycle is started.
In ST-BUS
®
mode, the falling edge of the frame measurement signal (Frame
Evaluation) is evaluated against the falling edge of the ST-BUS
®
frame pulse.
In GCI mode, the rising edge of Frame Evaluation is evaluated against the rising
edge of the GCI frame pulse. See Table 7 and Figure 1 for the description of
the Frame Alignment Register.
MEMORY BLOCK PROGRAMMING
The IDT72V73250 provides users with the capability of initializing the entire
Connection Memory block in two frames. To set bits 14 and 15 of every
Connection Memory location, first program the desired pattern in the Block
Programming Data Bits (BPD 1-0), located in bits 7 and 8 of the Control Register.
The block programming mode is enabled by setting the Memory Block
Program bit of the Control Register HIGH. When the Block Programming Enable
FUNCTIONAL DESCRIPTION
DATA AND CONNECTION MEMORY
All data that comes in through the RX inputs go through a serial-to-parallel
conversion before being stored into internal Data Memory. The 8 KHz frame
pulse (F32i) is used to mark the 125μs frame boundaries and to sequentially
address the input channels in Data Memory.
Data output on the TX streams may come from either the serial input streams
(Data Memory) or from the microprocessor (Connection Memory). In the case
that RX input data is to be output, the addresses in Connection Memory are used
to specify a stream and channel of the input. The Connection Memory is setup
in such a way that each location corresponds to an output channel for each
particular stream. In that way, more than one channel can output the same data.
In Processor Mode, the microprocessor writes data to the Connection Memory
locations corresponding to the stream and channel that is to be output. The lower
half (8 least significant bits) of the Connection Memory is output every frame until
the microprocessor changes the data or mode of the channel. By using this
Processor Mode capability, the microprocessor can access input and output
time-slots on a per-channel basis.
The two most significant bits of the Connection Memory are used to control
per-channel mode of the out put streams. Specifically, the MOD1-0 bits are used
to select Processor Mode, Constant or Variable delay Mode, and the high-
impedance state of output drivers. If the MOD1-0 bits are set to 1-1 accordingly,
only that particular output channel (8 bits) will be in the high-impedance state.
If however, the ODE input pin is LOW and the Output Standby Bit in the Control
Register is LOW, all of the outputs will be in a high-impedance state even if a
particular channel in Connection Memory has enabled the output for that
channel. In other words, the ODE pin and Output Stand By control bit are master
output enables for the device (See Table 3).
5
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