CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175
o
C for ceramic packages,
and below 150
o
C for plastic packages.
2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and V
LOGIC
shown in curves of Power Dissipation
vs Supply Voltages (see Performance Curves). The calculated T.P.D. is then located on the graph of Maximum Allowable Package Dissipation
vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated T.P.D. (See Performance Curves). For
instance, the combination of +15V, -15V, +5V, 0V (V+, V-, V
LOGIC
+, V
LOGIC
-) gives a T.P.D. of 350mW, the combination +15V, -15V, +15V,
0V gives a T.P.D. of 450mW.
3.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
V
SUPPLY
= ±15V, V
LOGIC
+ = 5V, V
LOGIC
- = GND
HA-4900-2
-55
o
C to 125
o
C
MIN
TYP
MAX
HA-4902-2
-55
o
C to 125
o
C
MIN
TYP
MAX
MIN
HA-4905-5
0
o
C to 75
o
C
TYP
MAX
UNITS
PARAMETER
INPUT CHARACTERISTICS
Offset Voltage (Note 4)
TEMP
(
o
C)
25
Full
-
-
-
-
-
-
-
-
V-
-
2
-
10
-
50
-
-
-
-
250
3
4
25
35
75
150
V
IO
+
0.3
V
IO
+
0.4
(V+) -
2.4
-
-
-
-
-
-
-
-
-
V-
-
2
-
10
-
50
-
-
-
-
250
5
8
35
45
150
200
V
IO
+
0.5
V
IO
+
0.6
(V+) -
2.6
-
-
-
-
-
-
-
-
-
V-
-
4
-
25
-
100
-
-
-
-
250
7.5
10
50
70
150
300
V
IO
+
0.5
V
IO
+
0.7
(V+) -
2.4
-
mV
mV
nA
nA
nA
nA
mV
mV
V
MΩ
Offset Current
25
Full
Bias Current (Note 5)
25
Full
Input Sensitivity (Note 6)
25
Full
Common Mode Range
Differential Input Resistance
TRANSFER CHARACTERISTICS
Large Signal Voltage Gain
Response Time (t
PD
(0))
(Note 7)
Response Time (t
PD
(1))
(Note 7)
Full
25
25
25
25
-
-
-
400
130
180
-
200
215
-
-
-
400
130
180
-
200
215
-
-
-
400
130
180
-
200
215
kV/V
ns
ns
2
HA-4900, HA-4902, HA-4905
Electrical Specifications
V
SUPPLY
= ±15V, V
LOGIC
+ = 5V, V
LOGIC
- = GND
(Continued)
HA-4900-2
-55
o
C to 125
o
C
MIN
TYP
MAX
HA-4902-2
-55
o
C to 125
o
C
MIN
TYP
MAX
MIN
HA-4905-5
0
o
C to 75
o
C
TYP
MAX
UNITS
PARAMETER
OUTPUT CHARACTERISTICS
Output Voltage Level
Logic “Low State” (V
OL
)
(Note 8)
Logic “High State” (V
OH
)
(Note 8)
Output Current
I
SINK
I
SOURCE
TEMP
(
o
C)
Full
Full
-
3.5
0.2
4.2
0.4
-
-
3.5
0.2
4.2
0.4
-
-
3.5
0.2
4.2
0.4
-
V
V
Full
Full
3.0
3.0
-
-
-
-
3.0
3.0
-
-
-
-
3.0
3.0
-
-
-
-
mA
mA
POWER SUPPLY CHARACTERISTICS
Supply Current, IPS (+)
Supply Current, IPS (-)
Supply Current, IPS (Logic)
Supply Voltage Range
V
LOGIC
+ (Note 2)
V
LOGIC
- (Note 2)
NOTES:
4. Minimum differential input voltage required to ensure a defined output state.
5. Input bias currents are essentially constant with differential input voltages up to
±9V.
With differential input voltages from
±9V
to
±15V,
bias cur-
rent on the more negative input can rise to approximately 500µA. This will also cause higher supply currents.
6. V
CM
= 0V. Input sensitivity is the worst case minimum differential input voltage required to guarantee a given output logic state. This parameter
includes the effects of offset voltage and voltage gain.
7. For t
PD
(1); 100mV input step, -10mV overdrive. For t
PD
(0); -100mV input step, 10mV overdrive. Frequency
≈
100Hz; Duty Cycle
≈
50%; Invert-
ing input driven. See Figure 1 for Test Circuit. All unused inverting inputs tied to +5V.
8. For V
OH
and V
OL
: I
SINK
= I
SOURCE
= 3.0mA. For other values of V
LOGIC
; V
OH
(Min) = V
LOGIC
+ -1.5V.
Full
Full
0
-15.0
-
-
+15.0
0
0
-15.0
-
-
+15.0
0
0
-15.0
-
-
+15.0
0
V
V
25
25
25
-
-
-
6.5
4
3.5
20
8
4
-
-
-
6.5
4
3.5
20
8
4
-
-
-
7
5
3.5
20
8
4
mA
mA
mA
Test Circuit and Waveform
+15V
+5V
OVERDRIVE
t
PD
(0)
t
PD
(1)
-
DUT
+
INPUT
V
OUT
100mV
V
TH
= 0V
100mV
V
TH
= 0V
-15V
OVERDRIVE
OUTPUT
1.5V
1.5V
t
PD
(1)
t
PD
(0)
t=0
t=0
FIGURE 1.
3
HA-4900, HA-4902, HA-4905
Schematic Diagram
R
1
500Ω
PR
1
200kΩ
Q
1
Q
3
D
4B
D
4A
Q
4C
D
45
Q
7
Q
19
Q
4
Q
5
R
16
540Ω
+IN
BIAS 1
Q
18
Q
17
Q
21
Q
22
D
35
-IN
Q
33
Q
34
Q
30
Q
20
Q
36
D
39
Q
37
Q
38
Q
28
R
9
4kΩ
R
10
4kΩ
Q
2
Q
11
R
2
13kΩ
Q
12
D
11A
R
3
1kΩ
Q
13
R
6
2.5kΩ
R
4
1kΩ
Q
14
R
7
2.5kΩ
R
5
360Ω
Q
15
Q
16
Q
26
Q
23
Q
24
Q
25
R
11
8kΩ
R
12
Q
29A
8kΩ
Q
29
D
29B
R
24
14kΩ
R
15
8kΩ
Q
10
R
20D
1kΩ
R
20C
1kΩ
R
20B
1kΩ
R
20A
1kΩ
R
21
1kΩ
M
N1
M
N3
M
N2
R
17
19kΩ
R
14
5kΩ
R
23
M
N5
100Ω
Q
31
R
22
100Ω
Q
32
OUT
M
N6
V
LOGIC
+
V+
R
18
664Ω
BIAS 2
Q
9D
BIAS 3 BIAS 4
D
9A
Q
9B
Q
9A
Q
9C
V
LOGIC
-
M
N4
V-
ONE FOURTH ONLY
Applying the HA-4900 Series Comparators
Supply Connections
This device is exceptionally versatile in working with most
available power supplies. The voltage applied to the V+ and V-
terminals determines the allowable input signal range; while the
voltage applied to the V
L
+ and V
L
- determines the output
swing. In systems where dual analog supplies are available,
these would be connected to V+ and V-, while the logic supply
and return would be connected to V
LOGIC
+ and V
LOGIC
-. The
analog and logic supply commons can be connected together
at one point in the system, since the comparator is immune to
noise on the logic supply ground. A negative output swing may
be obtained by connecting V
L
+ to ground and V
L
- to a negative
supply. Bipolar output swings (15V
P-P
, Max) may be obtained
using dual supplies. In systems where only a single logic supply
is available (+5V to 15V), V+ and V
LOGIC
+ may be connected
together to the positive supply while V- and V
LOGIC
- are
grounded. If an input signal could swing negative with respect
the V- terminal, a resistor should be connected in series with
the input to limit input current to < 5mA since the C-B junction of
the input transistor would be forward biased.
Power Supply Decoupling
Decouple all power supply lines with 0.01µF ceramic capacitors
to ground line located near the package to reduce coupling
between channels or from external sources.
Response Time
Fast rise time (<200ns) input pulses of several volts
amplitude may result in delay times somewhat longer than
those illustrated for 100mV steps. Operating speed is
optimized by limiting the maximum differential input voltage
applied, with resistor-diode clamping networks.
Typical Applications
Data Acquisition System
In this circuit the HA-4900 series is used in conjunction with
a D to A converter to form a simple, versatile, multi-channel
analog input for a data acquisition system. In operation the
processor first sends an address to the D to A, then the
processor reads the digital word generated by the
comparator outputs. To perform a simple comparison, the
processor sets the D to A to a given reference level, then
examines one or more comparator outputs to determine if
their inputs are above or below the reference. A window
comparison consists of two such cycles with 2 reference
levels set by the D to A. One way to digitize the inputs would
be for the processor to increment the D to A in steps. The D
to A address, as each comparator switches, is the digitized
level of the input. While stairstepping the D to A is slower
than successive approximation, all channels are digitized
during one staircase ramp.
Unused Inputs
Inputs of unused comparator sections should be tied to a
differential voltage source to prevent output “chatter.”
Crosstalk
Simultaneous high frequency operation of all other channels
in the package will not affect the output logic state of a given
channel, provided that its differential input voltage is
sufficient to define a given logic state (∆V
IN
≥ ±V
OS
). Low
level or high impedance input lines should be shielded from
other signal sources to reduce crosstalk and interference.
4
HA-4900, HA-4902, HA-4905
Window Detector
LATCH
D/A
MEMORY
INTERFACE
ANALOG
INPUTS
INTERFACE
The high switching speed, low offset current and low offset
voltage of the HA-4900 series makes this window detector
circuit extremely well suited to applications requiring fast,
accurate, decision-making. The circuit above is ideal for
industrial process system feedback controllers or “out-of-
limit” alarm indicators.
+15V
V
L
+
MICRO-
PROCESSOR
COMPARATORS
ANALOG INPUT MODULE
PROCESSOR
INPUT
+
HIGH
HIGH REF
-
+5.0V
Logic Level Translators
The HA-4900 series comparators can be used as versatile
logic interface devices as shown in the circuits above.
Negative logic devices may also be interfaced with
appropriate supply connections. If separate supplies are
used for V- and V
LOGIC
-, these logic level translators will
tolerate several volts of ground line differential noise.
+5.0V
+5V TO +15V
V
L
+
4.7kΩ
+
1/4
HA-4900
10kΩ
+
1/4
HA-4900
+5.0V
V+
1/2 HA-4900
-15V
IN
WINDOW
1/4 HD-74C02
LOW REF
+
LOW
-
Oscillator/Clock Generator
This self-starting fixed frequency oscillator circuit gives
excellent frequency stability. R
1
and C
1
comprise the
frequency determining network while R
2
provides the
regenerative feedback. Diode D
1
enhances the stability by
compensating for the difference between V
OH
and
V
SUPPLY
. In applications where a precision clock generator
up to 100kHz is required, such as in automatic test
equipment, C
1
may be replaced by a crystal.
V+
R
2
150kΩ
D
1
V+
-
1N914s
10kΩ
-
+
1/4
HA-4900
+
1/4
HA-4900
-
TTL TO CMOS
-
CMOS TO TTL
1N914
150kΩ
RS-232 To CMOS Line Receiver
This RS-232 type line receiver to drive CMOS logic uses a
Schmitt trigger feedback network to give about 1V input
hysteresis for added noise immunity. A possible problem in
an interface which connects two equipments, each plugged
into a different AC receptacle, is that the power line voltage
may appear at the receiver input when the interface
connection is made or broken. The two diodes and a 3W
input resistor will protect the inputs under these conditions.
+10V
4.7kΩ
3W
150kΩ
+
1/4
HA-4900
-
1
-
f
≈
-----------------------
2.1R
1
C
1
C
1
R
1
50kΩ
Schmitt Trigger
(Zero Crossing Detector With Hysteresis)
-
1/4
HA-4900
+
1N4001s
1kΩ
56kΩ
51kΩ
1kΩ
This circuit has a 100mV hysteresis which can be used in
applications where very fast transition times are required at
the output even though the signal input is very slow. The
hysteresis loop also reduces false triggering due to noise on
the input. The waveforms below show the trip points
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