32 Mbit (x8/x16) Concurrent SuperFlash
SST36VF3203 / SST36VF3204
SST36VF3201C / 1602C32Mb (x8/x16) Concurrent SuperFlash
Advance Information
FEATURES:
• Organized as 2M x16 or 4M x8
• Dual Bank Architecture for Concurrent
Read/Write Operation
– 32 Mbit Bottom Sector Protection
(in the smaller bank)
- SST36VF3203: 24 Mbit + 8 Mbit
– 32 Mbit Top Sector Protection
(in the smaller bank)
- SST36VF3204: 8 Mbit + 24 Mbit
• Single 2.7-3.6V for Read and Write Operations
• Superior Reliability
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
• Hardware Sector Protection/WP# Input Pin
– Protects 8 KWord in the smaller bank or, top or
bottom bank for 16 Mbit+16 Mbit, by driving WP#
low and unprotects by driving WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
array data
• Byte# Pin
– Selects 8-bit or 16-bit mode
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Chip-Erase Capability
• Block-Erase Capability
– Uniform 32 KWord blocks
• Erase-Suspend / Erase-Resume Capabilities
• Security ID Feature
– SST: 128 bits
– User: 256 Bytes
• Fast Read Access Time
– 70 ns
• Latched Address and Data
• Fast Erase and Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal V
PP
Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
• CMOS I/O Compatibility
• Conforms to Common Flash Memory Interface (CFI)
• JEDEC Standards
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF320x are 2M x16 or 4M x8 CMOS Concur-
rent Read/Write Flash Memory manufactured with SST’s
proprietary, high performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability com-
pared with alternate approaches. The devices write (Pro-
gram or Erase) with a 2.7-3.6V power supply and conform
to JEDEC standard pinouts for x8/x16 memories.
Featuring high performance Word-Program, these devices
provide a typical Program time of 7 µsec and use the Tog-
gle Bit, Data# Polling, or RY/BY# to detect the completion
of the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
devices significantly improve performance and reliability,
while lowering power consumption. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
CSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
To meet high-density, surface-mount requirements, these
devices are offered in 48-ball TFBGA and 48-lead TSOP
packages. See Figures 1 and 2 for pin assignments.
Read Operation
The Read operation is controlled by CE# and OE#; both
have to be low for the system to obtain data from the out-
puts. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in a high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 3).
Program Operation
Device Operation
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.
The Program operation is accomplished in three steps:
1. Software Data Protection is initiated using the
three-byte load sequence.
2. Address and data are loaded.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
See Figures 4 and 5 for WE# and CE# controlled Program
operation timing diagrams and Figure 19 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.
Auto Low Power Mode
These devices also have the
Auto Lower Power
mode
which puts them in a near standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the I
DD
active Read current to 4 µA typically.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
Concurrent Read/Write Operation
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank.
C
ONCURRENT
R
EAD
/W
RITE
S
TATE
Bank 1
Read
Read
Write
Write
No Operation
No Operation
Bank 2
No Operation
Write
Read
No Operation
Read
Write
Note:
For the purposes of this table, write means to perform Block-
or Sector-Erase or Program operations as applicable to the
appropriate bank.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
2
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Sector- (Block-) Erase Operation
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (50H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (30H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 9 and 10 for timing waveforms.
Erase-Suspend/Erase-Resume Operations
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs after
the Erase-Suspend command had been issued. Valid data
can be read from any sector or block that is not suspended
from an Erase operation. Reading at address location
within erase-suspended sectors/blocks will output DQ
2
tog-
gling and DQ
6
at “1”. While in Erase-Suspend mode, a Pro-
gram operation is allowed except for the sector or block
selected for Erase-Suspend. The Software ID Entry com-
mand can also be executed. To resume Sector-Erase or
Block-Erase operation which has been suspended, the
system must issue an Erase-Resume command. The
operation is executed by issuing a one-byte command
sequence with Erase Resume command (30H) at any
address in the last byte sequence.
Chip-Erase Operation
The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the “1” state. This is
useful when a device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com-
mands issued during the Chip-Erase operation are
ignored. See Table 7 for the command sequence, Figure 8
for timing diagram, and Figure 22 for the flowchart. When
WP# is low, any attempt to Chip-Erase will be ignored.
Write Operation Status Detection
These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ
7
), or Toggle Bit (DQ
6
) Read may
be simultaneous with the completion of the Write cycle. If
this occurs, the system may get an erroneous result, i.e.,
valid data may appear to conflict with either DQ
7
or DQ
6
. In
order to prevent spurious rejection if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
Reads are valid, then the Write cycle has completed, other-
wise the rejection is valid.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
3
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Ready/Busy# (RY/BY#)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to V
DD
via an external pull-up
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Toggle Bits (DQ
6
and DQ
2
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ
6
bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the
rising edge of sixth WE# (or CE#) pulse. DQ
6
will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ
6
will
toggle.
An additional Toggle Bit is available on DQ
2
, which can be
used in conjunction with DQ
6
to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ
2
)
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 7 for Toggle Bit timing dia-
gram and Figure 20 for a flowchart.
TABLE 1: W
RITE
O
PERATION
S
TATUS
Status
Normal
Standard
Operation Program
Standard
Erase
Erase-
Suspend
Mode
Read From
Erase
Suspended
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Program
DQ
7
DQ7#
0
1
DQ
6
Toggle
Toggle
1
DQ
2
No Toggle
Toggle
Toggle
RY/BY#
0
0
1
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (V
IH
) the device is in x16 data configuration: all
data I/0 pins DQ
0
-DQ
15
are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic “0”, the device is in x8 data con-
figuration: only data I/O pins DQ
0
-DQ
7
are active and con-
trolled by CE# and OE#. The remaining data pins DQ
8
-
DQ
14
are at Hi-Z, while pin DQ
15
is used as the address
input A
-1
for the Least Significant Bit of the address bus.
Data# Polling (DQ
7
)
When the devices are in an internal Program operation, any
attempt to read DQ
7
will produce the complement of the
true data. Once the Program operation is completed, DQ
7
will produce true data. During internal Erase operation, any
attempt to read DQ
7
will produce a ‘0’. Once the internal
Erase operation is completed, DQ
7
will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling
(DQ
7
) timing diagram and Figure 20 for a flowchart.
Data
Data
Data
1
DQ7#
Toggle
N/A
0
T1.1 1270
Note:
DQ
7,
DQ
6,
and DQ
2
require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
Data Protection
The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
4
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
These devices provide the JEDEC standard Software Data
Protection scheme for all data alteration operations, i.e.,
Program and Erase. Any Program operation requires the
inclusion of the three-byte sequence. The three-byte load
sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of the six-byte
sequence. The devices are shipped with the Software Data
Protection permanently enabled. See Table 7 for the spe-
cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within T
RC.
The contents of DQ
15
-DQ
8
can be V
IL
or
V
IH,
but no other value during any SDP command
sequence.
Hardware Block Protection
The devices provide hardware block protection which pro-
tects the outermost 8 KWord in the smaller bank or, top or
bottom bank for 16 Mbit +16 Mbit. The block is protected
when WP# is held low. When WP# is held low and a Block-
Erase command is issued to the protected black, the data
in the outermost 8 KWord/16 KByte section will be pro-
tected. The rest of the block will be erased. See Tables 3
and 4 for Block-Protection location.
A user can disable block protection by driving WP# high.
This allows data to be erased or programmed into the pro-
tected sectors. WP# must be held high prior to issuing the
Write command and remain stable until after the entire
Write operation has completed. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
Common Flash Memory Interface (CFI)
These devices also contain the CFI information to
describe the characteristics of the devices. In order to
enter the CFI Query mode, the system must write the
three-byte sequence, same as the Software ID Entry com-
mand with 98H (CFI Query command) to address
BK
X
555H in the last byte sequence. In order to enter the
CFI Query mode, the system can also use the one-byte
sequence with BK
X
55H on Address and 98H on Data Bus.
See Figure 12 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 8
through 10. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least T
RP,
any in-progress operation will terminate and
return to Read mode (see Figure 16) and all output pins
are set to High-Z. When no internal Program/Erase opera-
tion is in progress, a minimum period of T
RHR
is required
after RST# is driven high before a valid Read can take
place (see Figure 15).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
5
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