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UPD72852GB-8EU: 产品描述Interface Circuit, MOS, PQFP64, 10 X 10 MM, PLASTIC, LQFP-64; 产品类别无线/射频/通信电信电路; 文件大小270KB，共48页; 制造商NEC(日电)

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UPD72852GB-8EU概述

Interface Circuit, MOS, PQFP64, 10 X 10 MM, PLASTIC, LQFP-64

UPD72852GB-8EU规格参数

参数名称	属性值
是否Rohs认证	不符合
厂商名称	NEC(日电)
零件包装代码	QFP
包装说明	LFQFP,
针数	64
Reach Compliance Code	compliant
JESD-30 代码	S-PQFP-G64
JESD-609代码	e0
长度	10 mm
功能数量	1
端子数量	64
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LFQFP
封装形状	SQUARE
封装形式	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	NOT SPECIFIED
认证状态	Not Qualified
座面最大高度	1.6 mm
标称供电电压	3.3 V
表面贴装	YES
技术	MOS
电信集成电路类型	INTERFACE CIRCUIT
温度等级	COMMERCIAL
端子面层	TIN LEAD
端子形式	GULL WING
端子节距	0.5 mm
端子位置	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED
宽度	10 mm

UPD72852GB-8EU文档预览

DATA SHEET

MOS INTEGRATED CIRCUIT

PD72852

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

The

PD72852 is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.

The

PD72852 supports transfers of up to 400 Mbps and consumes less power than the

PD72850B. The

PD72852 is suitable for battery systems with an IEEE1394 interface.

FEATURES

• The two-port physical layer LSI complies with IEEE1394a-2000

• Fully interoperable with IEEE1394 std 1394 Link (FireWire

, i.LINK

)

• Meets Intel

Mobile Power Guideline 2000

• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-

speed concatenation, arbitration acceleration, fly-by concatenation

• Fully compliant with OHCI requirements

• Small package: 64-pin plastic LQFP

• Super low power: 68 mA (Operating mode)

: 115

A (Suspend mode)

• Data rate: 400/200/100 Mbps

• Supports PHY pinging and remote PHY access packets

• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)

• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency

• 64-bit flexible register incorporated in PHY register

• Electrically isolated Link interface

• Supports LPS/Link-on as part of PHY/Link interface

• External filter capacitors for PLL not required

• Extended Resume signaling for compatibility with legacy DV devices

• System power management by signaling of node power class information

• Cable power monitor (CPS) is equipped

ORDERING INFORMATION

Part number

Package

64-pin plastic LQFP (10 x 10)

PD72852GB-8EU

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. S14920EJ3V0DS00 (3rd edition)

Date Published March 2001 NS CP(K)

Printed in Japan

The mark

shows major revised points.

2000

PD72852

BLOCK DIAGRAM

CMC

PC0

PC1

PC2

SUS/RES

TpA0p

TpA0n

Cable

Port0

LREQ

LPS

DIRECT

SCLK

LKON

CTL0

CTL1

TpB0p

TpB0n

Arbitration

and Control

State Machine

Logic

Link

Interface

I/O

TpA1p

TpA1n

Cable

Port1

TpB1p

TpB1n

Receive Data

Decoder and

Retimer

Voltage

and

Current

Generator

Crystal

Oscillator

PLL

System

and

Transmit

Clock

Generator

TpBias0

TpBias1

RI1

RESETB

CPS

Cable

Power

Status

Transmit Data

Encoder

Data Sheet S14920EJ3V0DS

PD72852

PIN CONFIGURATION (Top View)

•

PD72852GB-8EU

64-pin plastic LQFP (10 x 10)

RESETB

DIRECT

DGND

IC(AL)

AGND

DGND

SCLK

IC(DL)

CTL0

CTL1

DGND

AGND

LREQ

LKON

TEST

SPD

LPS

TpBias1

TpA1p

TpA1n

TpB1p

TpB1n

AGND

TpBias0

TpA0p

TpA0n

TpB0p

TpB0n

AGND

RI1

AGND

CMC

DGND

IC(AL)

PC0

PC1

PC2

SUS/RES

CPS

Data Sheet S14920EJ3V0DS

PD72852

PIN NAME

AGND

CMC

CPS

CTL0

CTL1

D0-D7

DGND

DIRECT

IC(AL)

IC(DL)

LKON

LPS

LREQ

PC0-PC2

RESETB

RI1

SCLK

SPD

SUS/RES

TEST

TpA0n

TpA0p

TpA1n

TpA1p

TpB0n

TpB0p

TpB1n

TpB1p

TpBias0

TpBias1

: Analog GND

: Analog Power

: Configuration Manager Capable

: Cable Power Status

: Link Interface Control (bit 0)

: Link Interface Control (bit 1)

: Data Input/Output

: Digital GND

: PHY/Link Isolation Barrier Control Input

: Digital V

: Internally Connected (Low Clamped)

: Link-on Signal Output

: Link Power Status Input

: Link Request Input

: Power Class Set Input

: Power-on Reset Input

: Reference Power Set, Connect Resistor 1

: Link Control Output Clock

: Speed Select

: Suspend/Resume Function Select

: Test Pin (Low Clamped)

: Port 0 Twisted Pair Cable A Negative Phase I/O

: Port 0 Twisted Pair Cable A Positive Phase I/O

: Port 1 Twisted Pair Cable A Negative Phase I/O

: Port 1 Twisted Pair Cable A Positive Phase I/O

: Port 0 Twisted Pair Cable B Negative Phase I/O

: Port 0 Twisted Pair Cable B Positive Phase I/O

: Port 1 Twisted Pair Cable B Negative Phase I/O

: Port 1 Twisted Pair Cable B Positive Phase I/O

: Port 0 Twisted Pair Output

: Port 1 Twisted Pair Output

: Crystal Oscillator Connection XI

: Crystal Oscillator Connection XO

Data Sheet S14920EJ3V0DS

PD72852

CONTENTS

1. PIN

1.1

1.2

1.3

1.4

1.5

1.6

FUNCTIONS..................................................................................................................................... 7

Cable Interface Pins ........................................................................................................................ 7

Link Interface Pins........................................................................................................................... 7

Control Pins ..................................................................................................................................... 8

IC ....................................................................................................................................................... 8

Power Supply Pins .......................................................................................................................... 8

Other Pins ........................................................................................................................................ 8

2. PHY REGISTERS..................................................................................................................................... 9

2.1 Complete Structure for PHY Registers.......................................................................................... 9

2.2 Port Status Page (Page 000)......................................................................................................... 12

2.3 Vendor ID Page (Page 001) ........................................................................................................... 13

2.4 Vendor Dependent Page (Page 111 : Port_select 0001) ............................................................ 13

3. INTERNAL FUNCTION.......................................................................................................................... 14

3.1 Link Interface ................................................................................................................................. 14

3.1.1 Connection Method............................................................................................................................... 14

3.1.2 LPS (Link Power Status)....................................................................................................................... 14

3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins .................................................................................................... 14

3.1.4 SCLK..................................................................................................................................................... 14

3.1.5 LKON .................................................................................................................................................... 15

3.1.6 DIRECT................................................................................................................................................. 15

3.1.7 Isolation Barrier..................................................................................................................................... 15

3.2 Cable Interface............................................................................................................................... 17

3.2.1 Connections .......................................................................................................................................... 17

3.2.2 Cable Interface Circuit .......................................................................................................................... 18

3.2.3 Unused Ports ........................................................................................................................................ 18

3.2.4 CPS....................................................................................................................................................... 18

3.3 Suspend/Resume .......................................................................................................................... 18

3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 18

3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 18

3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 19

3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 19

3.4.2 PLL........................................................................................................................................................ 19

3.5

3.6

3.7

3.8

CMC ................................................................................................................................................ 19

PC0-PC2 ......................................................................................................................................... 19

RESETB .......................................................................................................................................... 19

RI1 ................................................................................................................................................... 19

4. PHY/LINK INTERFACE ......................................................................................................................... 20

4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface ............................................ 20

4.2 Link-on Indication.......................................................................................................................... 21

4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)....................................................... 22

4.3.1 CTL0, CTL1 .......................................................................................................................................... 22

4.3.2 LREQ .................................................................................................................................................... 22

4.3.3 SCLK Timing......................................................................................................................................... 26

Data Sheet S14920EJ3V0DS

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UPD72852GB-8EU

UPD72852GB-8EU概述

UPD72852GB-8EU规格参数

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