The Future of Analog IC Technology
24V, High Current
Synchronous Buck Converter
With +/-1.5A LDO and Buffed Reference
FEATURES
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Wide 5V to 24V Operating Input Range
10A Continuous Output Current
12A Peak Output Current
Built-in +/- 1.5A VTTLDO
Low R
DS
(ON) Internal Power MOSFETs
Proprietary Switching Loss Reduction
Technique
Internal Soft Start
Output Discharge
500kHZ Switching Frequency
OCP, OVP, UVP Protection and Thermal
Shutdown
VDDQ Adjustable from 0.604V to 5.5V
Laptop Computer
Tablet PC
Networking Systems
Server
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
NB675
DESCRIPTION
The NB675 provides a complete power supply
for DDR3, DDR3L and LPDDR2 memory with
the highest power density. It integrates a high
frequency synchronous rectified step-down
switch mode converter (VDDQ) with an 1.5A
sink/source LDO (VTT) and buffered low noise
reference (VTTREF).
The fully integrated Buck converter is able to
deliver 10A continuous output current and 12A
peak output current over a wide input supply
range with excellent load and line regulation.
The Buck converter employs the Constant-On-
Time (COT) control scheme, which provides
fast transient response and eases loop
stabilization.
The VTT LDO provides 1.5A sink/source
current capability and requires only 10uF
ceramic capacitance.
The VTTREF tracks VDDQ/2 with an excellent
1% accuracy.
Under voltage lockout is internally set as 4.5V.
An open drain power good signal indicates
VDDQ is within its nominal voltage range.
Full protection features include OCP, OVP, and
thermal shut down.
This part requires minimum number of external
components and is available in QFN21
(3mmx4mm) package.
APPLICATIONS
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
V
IN
5-21V
VIN
BST
SW
220nF
VDDQ
1.35V/10A
95
85
75
65
55
EN 1
EN 2
PG
FB
NB675
VDDQSEN
VCC
AGND
PGND
VTTREF
45
VTT
0.675V/2A
VINLDO
35
25
15
0.001
0.01
0.1
1
10
VTT
VTTSEN
220nF
LOAD CURRENT (A)
NB675 Rev. 1.0
1/14/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
1
NB675 –24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
ORDERING INFORMATION
Part Number*
NB675GL
Package
QFN21 (3mmx4mm)
Top Marking
NB675
*
For Tape & Reel, add suffix –Z (e.g. NB675GL–Z)
PACKAGE REFERENCE
TOP VIEW
NC
18
EN2
17
VCC
16
EN1
15
FB
14
PG
13
BST
1
19
VIN
12
VIN
SW
2
20
PGND
11
PGND
SW
3
21
PGND
10
PGND
4
5
6
7
8
9
VTTSEN
VTT
VDDQSEN
VTTREF
VINLDO
AGND
EXPOSED PAD
ON BACKSIDE
ABSOLUTE MAXIMUM RATINGS
(1)
Thermal Resistance
(5)
Supply Voltage V
IN
....................................... 24V
V
SW
...............................................-0.3V to 24.3V
V
SW
(30ns)..........................................-3V to 28V
V
SW
(5ns)............................................-6V to 28V
V
BST
................................................... V
SW
+ 5.5V
V
EN
............................................................... 12V
Enable Current I
EN (2)
................................ 2.5mA
All Other Pins ..............................–0.3V to +5.5V
(3)
Continuous Power Dissipation (T
A
=+25°)
QFN21 ..................................................... 2.5W
Junction Temperature ...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
QFN21 (3mmx4mm) ...............50 ...... 12 ...
°C/W
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to Page 13 of Configuring the EN Control.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature T
J
(MAX), the junction-to-
ambient thermal resistance
θ
JA
, and the ambient temperature
T
A
. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by P
D
(MAX)=(T
J
(MAX)-
T
A
)/θ
JA
. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
θ
JA
θ
JC
Recommended Operating Conditions
(4)
Supply Voltage V
IN
..............................5V to 22V
Output Voltage V
OUT
....................0.604V to 5.5V
Enable Current I
EN
....................................... 1mA
Operating Junction Temp. (T
J
). -40°C to +125°C
NB675 Rev. 1.0
1/14/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
2
NB675 –24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
ELECTRICAL CHARACTERISTICS
V
IN
= 12V, T
J
= 25°C, unless otherwise noted.
Parameters
Supply Current
Supply Current (Shutdown)
Supply Current (In S0 Mode)
Supply Current (In S3 Mode)
MOSFET
High-side Switch On Resistance
Low-side Switch On Resistance
Switch Leakage
Current Limit
Low-side Valley Current Limit
I
LIMIT
F
S
T
OFF
V
OVP
T
OVPDEL
V
UVP
T
UVPDEL
V
REF
I
FB
T
SS
VIL
EN
V
EN-HYS
I
EN
VCC
Vth
VCC
HYS
V
EN
= 2V
V
EN
= 0V
10
11
12
A
HS
RDS-ON
LS
RDS-ON
SW
LKG
T
J
=25°C
T
J
=25°C
V
EN
= 0V, V
SW
= 0V
25
9
0
1
mΩ
mΩ
μA
Symbol
I
IN
I
IN
I
IN
Condition
V
EN
=
0V
V
EN1
=
V
EN1
=2V,
V
FB
= 0.65V, I
VTT
=
0A
V
EN1
=
0V, V
EN2
=
2V,
V
FB
= 0.65V
Min
Typ
0
300
160
400
190
Max
1
500
220
Units
μA
μA
μA
Switching frequency and minimum off time
Switching frequency
Minimum Off Time
(6)
OVP Threshold
OVP Delay
UVP Threshold
UVP Delay
Reference And Soft Start
Reference Voltage
Feedback Current
Soft Start Time
Enable And UVLO
Enable Input Low Voltage
Enable Hysteresis
Enable Input Current
VCC Under Voltage Lockout
Threshold Rising
VCC Under Voltage Lockout
Threshold Hysteresis
1.15
1.25
100
3
0
4.5
500
1.35
V
mV
μA
4.85
V
mV
598
V
FB
= 0.604V
604
10
1.6
610
50
1.95
mV
nA
ms
400
250
125
55
500
300
130
2.5
60
12
600
350
135
65
kHz
ns
%V
REF
μs
%V
REF
μs
Over-voltage and Under-voltage Protection
NB675 Rev. 1.0
1/14/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
3
NB675 –24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
ELECTRICAL CHARACTERISTICS
(continued)
V
IN
= 12V, T
J
= 25°C, unless otherwise noted.
Parameters
VCC Regulator
VCC Regulator
VCC Load Regulation
Power Good
FB Rising (Good)
FB Falling (Fault)
FB Rising (Fault)
FB Falling (Good)
Power Good Low to High Delay
Power Good Sink Current
Capability
Power Good Leakage Current
VTTREF Output
VTTREF Output Voltage
Output Voltage tolerance to
VDDQ
Current Limit
VTT LDO
VTT Output Voltage
VTT tolerance to VTTREF
Source Current Limit
Sink Current Limit
Thermal Protection
Thermal Shutdown
(6)
Thermal Shutdown Hysteresis
Note:
6) Guaranteed by design.
Symbol
Condition
Min
Typ
Max
Units
V
CC
Icc=8mA
4.8
5.1
5
5.3
V
%
PG
Vth-Hi
PG
Vth-Lo
PG
Vth-Hi
PG
Vth-Lo
PG
Td
V
PG
I
PG_LEAK
V
TTREF
I
VTTREF
<0.1mA,
1V<V
DDQ
<1.4V
I
VTTREF
<10mA,
1V<V
DDQ
<1.4V
I
LIMIT_VTTREF
V
TT
-10mA<I
VTT
<10mA,
1V<V
DDQ
<1.4V
-1A<I
VTT
<1A,
1V<V
DDQ
<1.4V
I
LIMIT_SOUCE
I
LIMIT_SINK
-20
-45
48.2%
48%
10
Sink 4mA
V
PG
= 3.3V
95
85
115
105
450
0.4
1
μs
V
μA
%V
REF
V
DDQSEN
/2
50%
50%
15
V
TTREF
20
45
1.8
1.6
mV
mV
A
A
51.8%
52%
mA
T
SD
150
25
°C
°C
NB675 Rev. 1.0
1/14/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
4
NB675 –24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER
PIN FUNCTIONS
PIN #
1
Description
Bootstrap. A capacitor connected between SW and BST pins is required to form a
BST
floating supply across the high-side switch driver.
Switch Output. Connect this pin to the inductor and bootstrap capacitor. This pin is
driven up to the VIN voltage by the high-side switch during the on-time of the PWM
duty cycle. The inductor current drives the SW pin negative during the off-time. The on-
SW
resistance of the low-side switch and the internal diode fixes the negative voltage. Use
wide and short PCB traces to make the connection. Try to minimize the area of the SW
pattern.
Buffered VTT reference output. Decouple with a minimum 0.22μF ceramic capacitor as
VTTREF close to the pin as possible. X7R or X5R grade dielectric ceramic capacitors are
recommended for their stable temperature characteristics.
Buck regulator output voltage sense. Connect this pin to the output capacitor of the
VDDQSEN
regulator directly
VINLDO
VTT LDO regulator input. Connect VINLDO to VDDQ in typical application.
VTT LDO output. Decouple with a minimum 10uF ceramic capacitor as close to the pin
VTT
as possible. X7R or X5R grade dielectric ceramic capacitors are recommended for their
stable temperature characteristics.
Analog ground. The internal reference is referred to AGND. Connect the GND of the
AGND
FB divider resistor to AGND for better load regulation.
VTTSEN VTT output sense. Connect this pin to the output capacitor of the VTT regulator directly
PGND
Power Ground. Use wide PCB traces and multiple vias to make the connection.
Supply Voltage. The VIN pin supplies power for internal MOSFET and regulator. The
NB675 operate from a +5V to +22V input rail. An input capacitor is needed to decouple
the input rail. Use wide PCB traces and multiple vias to make the connection.
Power good output, the output of this pin is an open drain signal and is high if the
output voltage is higher than 95% of the nominal voltage. There is a delay from FB
≥
95% to PG goes high.
Feedback. An external resistor divider from the output to GND, tapped to the FB pin,
sets the output voltage. Place the resistor divider as close to FB pin as possible. Avoid
vias on the FB traces. It is recommend to set the current through FB resistors around
10uA.
Enable. EN1 and EN2 are digital inputs, which are used to enable or disable the
internal regulators. Once EN1=EN2=1, the VDDQ regulator, VTT LDO and VTTREF
output will be turned on; when EN1=0 and EN2=1, the VDDQ regulator and VTTREF
are active while VTT LDO is off; all the regulators will be turned off when EN1=EN2=0.
Internal 5V LDO output. The driver and control circuits are powered from this voltage.
Decouple with a minimum 1µF ceramic capacitor as close to the pin as possible. X7R
or X5R grade dielectric ceramic capacitors are recommended for their stable
temperature characteristics.
Enable. EN1 and EN2 are digital inputs, which are used to enable or disable the
internal regulators. Once EN1=EN2=1, the VDDQ regulator, VTT LDO and VTTREF
output will be turned on; when EN1=0 and EN2=1, the VDDQ regulator and VTTREF
are active while VTT LDO is off; all the regulators will be turned off when EN1=EN2=0.
Not connected.
Name
2, 3
4
5
6
7
8
9
10,11
Exposed
Pad 20,21
12
Exposed
Pad 19
13
VIN
PG
14
FB
15
EN1
16
VCC
17
18
EN2
NC
NB675 Rev. 1.0
1/14/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
5
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