MK1493-02A
Networking/PCI Clock Generator
Description
The MK1493-02A is a general purpose clock generator
that provides an integrated clocking solution for
PCI/Networking applications. It provides two pairs of
differential CPU clocks, four PCI clocks, seven PCI_X
clocks, two reference clocks, additional clock selectable
from REF/50 MHz, and six pairs of SSTL2 DDR at
2.5 V.
All complementary outputs operate only from
a 2.5 V power supply.
Input/Output Features
•
Packaged in 56-pin TSSOP package
•
2 - Pairs of differential CPU clocks (differential
•
•
•
•
•
•
•
•
•
•
•
current mode)
4 - PCI @ 3.3 V
7 - PCI_X @ 3.3 V
2 - REF @ 3.3 V, Fixed
6 - Pairs of differential SSTL2 DDR @ 2.5 V
1 - REF/50 MHz, selectable
Spread spectrum for EMI control
Supports SMBUS index read/write and blocks
read/write operations
Uses external 25 or 50 MHz crystal or clock
CPU output jitter <125 ps
PCI cycle to cycle output jitter <250 ps
DDR cycle to cycle output jitter <150 ps
Block Diagram
PLL2
X1
XTAL
OSC
X2
PLL1
Spread
Spectrum
CPU
Divider
PCI
Divider
OE
FREQSEL
FS (3:0)
SDATA
SCLK
CLK_STOPB
PCI_STOPB
SSEN
4
50MHz/REF2
External
capacitor
required with crystal for
accurate timing of clock
2
REF(0:1)
Stop
Delay
2
2
7
CPUCLKT (1:0)
CPUCLKC (1:0)
PCI_XCLK (6:0)
Stop
Delay
Control
Logic
Config.
Reg.
AGP
Divider
DDR
Divider
Stop
Stop
Delay
Delay
4
6
6
PCI (3:0)
DDRT (5:0)
DDRC (5:0)
IREF
MDS 1493-02A C
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 020204
tel (408) 297-1201
●
www.icst.com
MK1493-02A
Networking/PCI Clock Generator
Pin Assignment
VDDAND
X1
X2
REF2_50M
VDDREF
VSSREF
FREQSEL_REF0
REF1
SCL
SDA
PCI_XSTPB
CLKSTPB
PCI0
PCI1
PCI2
PCI3
VDDPCI
VSSPCI
VSSPCI_X2
VDDPCI_X2
FS0_PCI_X0
FS1_PCI-X1
FS2_PCI_X2
FS3_PCI_X3
SSEN_PCI_X4
PCI_X5
PCI_X6
VSSPCI_X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSSAND
IREF
OE
CPUT0
CPUC0
VSSCPU
VDDCPU
CPUT1
CPUC1
VSSDR0
VDDDR0
DDRT0
DDRC0
DDRT1
DDRC1
VSSDR1
VDDDR1
DDRT2
DDRC2
DDRT3
DDRC3
VDDDR2
VSSDR2
DDRT4
DDRC4
DDRT5
DDRC5
VDDPCI_X1
56 pin 240mil 0.50 mm pitch TSSOP
Functionality Table
F
IN
MHz
50
50
25
25
25
1
25
25
25
25
25
25
25
1
FS3
0
0
0
0
1
1
1
1
1
1
1
1
FS2
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
CPUCLK
MHz
33
100
33
33
100
1
200
133
133
133
150
125
166
DDR
MHz
33
133
33
33
200
1
200
133
133
133
150
125
166
PCI
MHz
33
33
33
33
66
1
66
33
33
66
33
33
33
PCI_X
MHz
33
33
33
133
33
1
33
66
33
66
33
33
33
Default start Output Clock settings,
33M=33.33 MHz, 66M=66.66 MHz, 133M=133.33 MHz.
MDS 1493-02A C
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 020204
tel (408) 297-1201
●
www.icst.com
MK1493-02A
Networking/PCI Clock Generator
Pin Descriptions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin
Name
VDDAND
X1/CLK
X2
REF2_50M
VDDREF
VSSREF
FREQSEL_REF0
REF1
SCL
SDA
PCI_XSTPB
CUP_STPB
PCI0
PCI1
PCI2
PCI3
VDDPCI1
VSSPCI1
VSSPCI_X2
VDDPCI_X2
FS0_PCI_X0
FS1_PCI-X1
FS2_PCI_X2
FS3_PCI_X3
SSEN_PCI4
PCI_X5
PCI_X6
VSSPCI_X1
VDDPCI_X1
DDRC5
DDRT5
DDRC4
DDRT4
VSSDR2
VDDDR2
DDRC3
Pin
Type
Power
XI
XO
Output
Power
Power
I/O
Output
I/O
Input
Input
Input
Output
Output
Output
Input
Power
Power
Power
Power
I/O
I/O
I/O
I/O
I/O
Output
Output
Power
Power
Output
Output
Output
Output
Power
Power
Output
Pin Description
Analog and digital power supply 3.3 V.
Crystal connection/input clock. Connect to a 25 MHz fundamental mode crystal.
Connect to a 25 MHz fundamental mode crystal or leave unconnected if X1 is a
REF2 or 50 MHz output.
Power supply for REF outputs.
Ground for REF outputs.
Input
frequency select input pin for 50 MHz/ REF2 (0=50 MHz select, 1=REF2
select).
Output
- REF0.( Internal Pull up resistor of 120K ohms see for page 21)
REF1 clock output.
Clock pin for SMBUS circuitry. 5 V tolerant.
Data pin for SMBUS circuitry. 5 V tolerant.
Asynchronous input Stops all PCI_XCLK at logic level 0 when pulled low.( Internal
pull up resistor 120K)
Asynchronous input halts CPU , DDR and PCI clocks at logic O when driven low. S.
(Internal pull up resistor 120K see page 21)
PCI Output clock 0.
PCI Output clock 1.
PCI Output clock 2.
PCI Output clock 3.
Power supply for PCI clocks.
Ground supply for PCI clocks.
Ground for PCI_X clocks.
Power supply for PCI_X clocks.
FS0 input/PCI_X0 output. (Internal Pull Down resistor 120K , see page 21).
FS1 input/PCI_X1 output. (Internal Pull Down resistor 120K , see page 21)
FS2 input/PCI_X2 output. (Internal Pull Down resistor 120K , see page 21).
FS3 input/PCI_X3 output. (Internal Pull up resistor 120K , see page 21).
Spread spectrum enable (0=SS disabled, 1=enabled). PCI clock output. (Internal pull
down resistor 120K see page 21)
PCI_X clock output.
PCI_X clock output.
Ground for PCI clocks.
Power supply for PCI clocks.
Complementary clock output of DDRT5.
True clock output of DDRT5.
Complementary clock output of DDRT4.
True clock output of DDRT4.
Ground for DDR clocks.
Power supply for DDR clocks (2.5 V only for complementary outputs).
Complementary clock output of DDRT3.
MDS 1493-02A C
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 020204
tel (408) 297-1201
●
www.icst.com
MK1493-02A
Networking/PCI Clock Generator
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Pin
Name
DDRT3
DDRC2
DDRT2
VDDDR1
VSSDR1
DDRC1
DDRT1
DDRC0
DDRT0
VDDDR0
VSSDR0
CPUC1
CPUT1
VDDCPU
VSSCPU
CPUC0
CPUT0
OE
IREF
VSSAND
Pin
Type
Output
Output
Output
Power
Power
Output
Output
Output
Output
Power
Power
Output
Output
Power
Power
Output
Output
Input
Output
Power
True clock output of DDRT3.
Pin Description
Complementary clock output of DDRT2.
True clock output of DDRT2.
Power supply for DDR clocks 2.5 V only for complementary outputs.
(Can use 3.3 V supply for single ended outputs)
Ground for DDR clocks.
Complementary clock output of DDRT1.
True clock output of DDRT1.
Complementary clock output of DDRT0.
True clock output of DDRT0.
Power supply for DDR clocks 2.5 V only for complementary outputs).
(Can use 3.3 V supply for single ended outputs)
Ground for DDR clocks.
Complementary CPU clock output.
True CPU clock output.
Power supply for CPU Clocks 3.3 V.
Ground for CPU clocks.
Complementary CPU clock output.
True CPU clock output.
Enables all outputs when high, tri-state outputs when low. Pull-up.
A precision resistor connected to ground establishes the external reference current.
Analog and digital ground power supply.
MDS 1493-02A C
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 020204
tel (408) 297-1201
●
www.icst.com
MK1493-02A
Networking/PCI Clock Generator
General SMBUS Serial Interface Info
General SM-Bus Serial Interface
Information
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the beginning byte location =
N
ICS clock will
acknowledge
Controller sends Byte Count
X
ICS clock will
acknowledge
Controller (host) starts sending Byte
N through Byte
N+X-1
ICS clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
Controller (host) will send a start bit
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the beginning Byte location =
N
ICS clock will
acknowledge
Controller (host) will send a repeat start bit
Controller (host) sends the read address Byte D3
(H)
ICS clock will
acknowledge
ICS clock will send the data Byte count = X
ICS clock sends Byte
N
ICS clock sends Byte
N+X-1
Controller (host) will need to acknowledge each Byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
T
Slave
Address D2
(H)
Controller (Host)
T
Slave Address
D2
(H)
starT bit
WR
=0
ICS (Slave/Receiver)
ICS (Slave/Receiver)
starT
WR
ACK
Beginning Loc = N
ACK
ACK
RT
ACK
Slave Address
D2
(H)
repeat
starT
RD
=1
ACK
ACK
Data Byte Count=X
ACK
O
O
O
ACK
O
ACK
O
O
N
P
NAK
stoP bit
X
B
Y
T
E
S
Beginning Byte N
O
O
O
Byte N + X - 1
Beg Location = N
Data Byte Count = X
ACK
Beginning Byte N
O
O
O
Byte N + X - 1
P
stoP
X Byte
MDS 1493-02A C
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 020204
tel (408) 297-1201
●
www.icst.com
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