USING THE IDT79R3051™ AND IDT79R3081™ WITH THE HP16500 LOGIC ANALYZER
USING THE IDT79R3051
™
AND
THE IDT79R3081
™
WITH THE
HP16500 LOGIC ANALYZER
APPLICATION NOTE AN-111
APPLICATION
NOTE
AN-111
Integrated Device Technology, Inc.
Supplement to Application Note AN-93
By Gary Szilagyi
INTRODUCTION
In Application Note-93, the use of IDT's 7RS364
disassembler with the HP16500 Logic Analyzer for the
IDT79R3051
TM
RISController
TM
family of CPUs was dis-
cussed in detail. However, the original versions of the
disassembler were form-fitted for the R3000 CPU interface of
a 32-bit non-multiplexed bus design. In order to accommodate
the high level of integration on-board the R3051, including the
4kB–8kB of instruction cache, 2kB of data cache, 4-deep read
and write buffers and the R3000A execution engine—all in a
single 84-pin package, the 32-bit bus required multiplexing
address and data pins. Although the original versions of the
disassembler remain compatible with the new family of IDT's
RISControllers, an effort was made to simplify the interface
between R3051 and the disassembler to accommodate simple
triggering schemes, as well as future IDT embedded control-
lers that continue in the path of the R3051 family.
THE IDT7RS364 DISASSEMBLER AND THE
IDTR3051
The IDT7RS364 Disassembler consists of a software pack-
age that greatly eases the task of debugging software on the
IDTR3051 family of CPUs. The HP16500 allows the capture
of executed hex/binary machine opcodes in a typical Logic
Analyzer State Trace Listing format with the ability to decode
and display the acquisitions in the R3000 assembly code
mnemonic format, as seen in Figure 1. Thus, the engineer
does not have to resort to look-up tables, and can effectively
determine the exact processor state for easy software debug-
ging.
The original versions of the disassembler were form-fitted
to the R3000 CPU interface. Although the derivative products
of the IDT R3051 family are compatible, the
RD
and
WR
signals used for data acquisitions by the disassembler pack-
age causes some confusion during a high-speed burst read.
As discussed in Application Note AN-93, the work-around was
to create a more complex read strobe in order to capture a
four- word burst read by setting up a trigger mechanism on the
HP16500 that looks like: [(
SysClk
==↑ ) AND [(
ACK
== 0) OR
RDCEN
== 0)]. However, this is only applicable to systems
that bring the
ACK
signal LOW at precisely the same time the
RDCEN
is LOW, or that don't bring it LOW at all during a four
word burst read. If, for instance, the
ACK
signal triggered in
the phase between two successive
RDCEN
s, a duplicated
capture would occur. The disassembler was modified a
second time to remedy this situation. In a read cycle, the
RD
pin will be asserted LOW for the entire cycle and the
RDCEN
signal toggles to successfully pass each of the four words
across the bus. The newest version of the disassembler
State/Timing E
Markers
Off
Label>
Base>
-61FC00000
-51FC00004
-41FC00220
-31FC00224
-21FC00228
-11FC0022C
01FC00230
11FC00234
21FC00238
31FC0023C
400000000
51FC00240
600000004
71FC00244
800000000
91FC00248
Listing 1
Invasm
Print
Run
ADDR
Hex
R3000 Mnemonic
hex
STAT
Hex
Time
Absolute
J 0x1FC00220
0010
0 s
NOP 0010
760 ns
LUI v0,0x0010 0010
1.52 us
MTCO v0,$12 0010
2.24 us
MTC0 zero,$13 0010
3.00 us
LUI v0,0xA000 0010
3.76 us
LUIt0,0xAAAA 0010
4.52 us
ORI t0,t0,0x5555 0010
5.24 us
SW t0,0x0000(v0) 0010
6.00 us
SW zero,0x0004(v0) 0010
6.76 us
STORE DATA 0xAAAA5555 0000
7.40 us
LW t1,0x0000(v0) 0010
7.88 us
STORE DATA 0x00000000 0000
8.52 us
NOP 0010
9.00 us
LOAD DATA 0xAAAA5555 0010
9.64 us
B 0x1FC00258 0010
10.32 us
Figure 1. R3051 Address/Data Trace List on a Logic Analyzer
The IDT Logo is a registered trademark and RISController, IDT79R3051 and IDT79R3081 are trademarks of Integrated Device Technology, Inc.
©1996
Integrated Device Technology
2948/-
2/96
207
USING THE IDT79R3051™ AND IDT79R3081™ WITH THE HP16500 LOGIC ANALYZER
APPLICATION NOTE AN-111
begins "LOAD" captures not on
RD
, but rather upon the
RDCEN
.
For interleaved memory systems that do not toggle the
RDCEN
pin, please refer to section "Hazards" for more details. During
a write cycle, it triggers upon the rising edge (from LOW-to-
HIGH) of the
WR
signal. Thus, the newest revision of the
disassembler now expects the
RDCEN
and the
WR
signals as
clocks to strobe the address and data into the HP16500, as
well as the
WR
, DIAG_1 and DIAG_0 to verify and decode the
processor status
INTERFACING THE HP16500 TO THE '385
EVALUATION BOARD
In order to insure proper operation of the disassembler, the
correct interface between the R305x target system and the
HP16500 must be available. The disassembler requires a
particular pinout setup on the logic analyzer's five 16-channel
probe pod sets. The interface protocol must be followed for
correct interpretation of the address, data, and status lines by
the pre-processor. Table 1 displays the default pod connec-
tions that the HP16500 expects (same setup for the 7RS385
evaluation board). This information is stored on disk in the
configuration file "DIS_305x_E". When loaded, this file not
only loads the disassembler, but also all the state and timing
information, including the default pod connections expected
at the system interface.
Application Note-93 discusses in detail the interface be-
tween typical R305x based systems and the logic analyzer.
Rather than repeat that discussion, the interface between the
7RS385 Evaluation board and the disassembler requires
some elaboration. For instance, the '385 Hardware User's
Manual shows the connections to be made from the board's
five 20-pin logic analyzer sockets and the logic analyzer's five,
16-channel pods. Note however that in section 2–5 of the '385
Hardware User's Manual, the connections on the status pod
(pod#5) are incorrect. In order to be consistent with the
protocol of the disassembler, some of the pins need to be
connected as follows:
• WR (J12 pin #17) needs to be on pod #5 channel #4
• RDCEN (J12 pin #14) needs to be on pod #5 channel #5
The disassembler also requires status lines for determining
processor status:
WR
,
RDCEN
, DIAG_1, and DIAG_0. The
WR
signal distinguishes between read and write cycles. The
RDCEN
pin is used to identify a false trigger for applications
that assert the
RDCEN
signal during writes. In order to avoid
a duplicate capture, the
RDCEN
signal is polled to determine
if it was the cause of the acquisition. If it was, then a trigger-
Table 1. R3051 Default Pod Connections on the HP16500 Logic Analyzer
POD
chan
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NClk
5
sig
X
X
X
Diag_1
(2)
X
Diag_0
X
X
X
X
POD
chan
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MClk
4
sig
A/D(31)
A/D(30)
A/D(29)
A/D(28)
A/D(27)
A/D(26)
A/D(25)
A/D(24)
A/D(23)
A/D(22)
A/D(21)
A/D(20)
A/D(19)
A/D(18)
A/D(17)
A/D(16)
POD
chan
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LClk
3
sig
A/D(15)
A/D(14)
A/D(13)
A/D(12)
A/D(11)
A/D(10)
A/D(9)
A/D(8)
A/D(7)
A/D(6)
A/D(5)
A/D(4)
A/D(3)
A/D(2)
A/D(1)
A/D(0)
POD
chan
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
KClk
2
sig
A(31)
A(30)
A(29)
A(28)
A(27)
A(26)
A(25)
A(24)
A(23)
A(22)
A(21)
A(20)
A(19)
A(18)
A(17)
A(16)
POD
chan
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
JClk
1
sig
A(15)
A(14)
A(13)
A(12)
A(11)
A(10)
A(9)
A(8)
A(7)
A(6)
A(5)
A(4)
Addr(3)
Addr(2)
RDCEN
WR
X
X
X
X
BEN(1)
BEN(2)
WR
RDCEN
NOTES:
1. Master Clock Format: N↑ + M↑ (default for the 7RS385 Evaluation Board setup)
2. POD5(12) is Diag_1 and POD5(10) is Diag_0 (Diag pins are not latched on the 7RS385 Eval Board) . If running uncached, then Diag_1 MUST be grounded
(GND), and Diag_0 is not used by disassembler.
3. A(31:4) are connected to the Address Latch outputs. The rest of the signals are connected to R3051 outputs. X’s denote unused probes that can be
assigned by the user.
208
USING THE IDT79R3051™ AND IDT79R3081™ WITH THE HP16500 LOGIC ANALYZER
APPLICATION NOTE AN-111
error message, “T.E”, and the store instruction along with the
write data on the bus is displayed (e.g. "T.E. (STORE
0xxxxxxxxx)). The diagnostic pin DIAG_1 distinguishes if the
external memory read was cacheable, and if so, determines
with DIAG_0 if it was an instruction or data read. Note that for
the newest IDT embedded controller, the R3081, DIAG_1 is
defined during writes, yielding cache information for “STORE”
instructions.
A second version of the disassembler,
“DIS_3081”, exploits this feature for external cache support.
By defining the DIAG_1 pin during writes, the CPU will signal
whether the data being written was retained in the on-chip
data cache. Keep in mind that the DIAG_0 pin remains
undefined during write cycles. This information is extremely
helpful to the programmer to determine the processor's state
when tracing through the software.
The diagnostic pins on the '385 board are
NOT LATCHED,
and therefore are time-multiplexed pins. Thus, the user must
either latch these pins with an external latch as seen in Figure
2 or proper decoding of cached code, or connect both diag-
nostic pins to GND. Although the disassembler is capable of
interpreting the bus transactions of cached code, keep in mind
that all logic analyzers and disassemblers can only capture
external CPU memory accesses. The R3051 has large
internal caches, and is capable of running much of its code
from within. In order for the disassembler to accurately reflect
the entire instruction/data flow, the R3051 must be ran
uncached. For more information regarding running cached
code and data, please refer to Application Note AN-93 for a
complete discussion.
Wr
DIAG_1
DIAG_0
FCT373
or
FCT841
LATCH
RdCache
Latched
DIAG_1
Latched
DIAG_0
ALE
R3051 Outputs
Logic Analyzer Probes
Figure 2. R3051 Address/Data Trace List on a Logic Analyzer
System
Configuration
Cancel
Master Frame
A
B
C
RS-232C
PATTERN GEN
HP-IB
LOADING AND RUNNING THE
DISASSEMBLER
Included in the software package are two files. The first is
the disassembler application "DIS_305x". The second is the
setup file, "DIS_305x_E", containing all the state and timing
information required by the disassembler, as well as the
assigned pod connections expected by the HP16500 for the
R305x target system.
After the HP operating system boots up completely, the
system configuration screen as shown in Figure 3 should be
displayed. To load the disassembler into the HP16500, the
following steps must be taken:
1. Insert the disassembler diskette into the front disk drive.
2. Select the “Configuration” field as shown in Figure 3. A
pop-up menu with options will appear. Choose the “Front
Disk” under the pop-up menu.
3. A new screen will appear that looks like Figure 4. Select
the “Load” and “State/Timing” fields, and load in the
configuration file “Dis_305x_E” by selecting “Execute” as
shown in Figure 4.
The HP16500 will then load the disassembler, as well as all
the state and timing information and the expected pin-configu-
ration as shown in Table 1 previously. Once the disassembler
application and setup files are loaded into the HP, the logic
analyzer is ready to set trace conditions for data acquisition.
D
E STATE/TIMING
Figure 3. HP16500 Screen Display
System
Front Disk
Cancel
Load
State/Timing_E
from file
DIS_305x_E
Execute
Filename
DIS_3051
DIS_3051_E
File Type
inverse_assm
16510B_config
File Description
R305x Inverse Assembler
R305x Config file
Figure 4. HP16500 Load Screen Display
209
USING THE IDT79R3051™ AND IDT79R3081™ WITH THE HP16500 LOGIC ANALYZER
APPLICATION NOTE AN-111
With the application files loaded, the disassembler is al-
most ready to be triggered by the target system. Follow the
steps below that describe how to run and trigger the
disassembler package:
1. Select the “System” field as shown in Figure 4. A pop-up
menu will appear with the option of “State/Timing”. Choose
this field to enter the state and timing mode of acquisition.
2. A new window will appear that is shown in Figure 5. Under
the “Configuration” menu lies options that allow the user to
set display or change the current configuration of the
interface, clocks, and pod connections.
3. Trigger the HP16500.
State/Timing E
Configuration
Cancel
Run
Analyzer 1
Name:
Type:
R3051
State
Type:
Analyzer 2
Off
Unassigned Pods
Pod 1
Pod 2
Pod 3
Pod 4
Pod 5
Once triggered, the logic analyzer will begin its acquisition,
and go directly to the “Listing” field. The addresses and
disassembled data will be displayed. Note however that the
displayed disassembly may be incorrect. This is due to an
"unsynchronized" system. The captured data needs to be
synchronized with the logic analyzer's display to insure cor-
rect disassembly of the bus. The problem of unsynchronized
captures arises due to the incomplete status of the processor
state for data loads. As a result, when an instruction fetch is
scrolled to the top of the screen, and a load data is displayed,
but the corresponding load instruction was "cut off" or scrolled
off the screen, the disassembler software looses it reference
point by which it identifies the load data. As a result, the load
data may be decoded incorrectly as an instruction as seen in
Figure 6. Notice in this Figure the instruction on line -2. It was
disassembled as an instruction instead of as a data load. Also
notice the address of the instruction in the sequence of the four
word fetch to main memory. This is an unsynchronized
display because the corresponding load instruction was scrolled
off the top of the display, and due to the way the disassembler
interprets and tags the load datas, the reference point was
lost. As a result, the load data was interpreted and decoded
as an instruction. As shown in Figure 7, the correctly synchro-
nized system has the load instruction displayed at the top of
the screen (identified by its address), and the load data is
interpreted correctly.
Figure 5. HP16500 State/Timing Mode Display
State/Timing E
Markers
Off
Label>
Base>
Listing 1
Invasm
Print
Run
ADDR
Hex
R3000 Mnemonic
hex
STAT
Hex
Time
Absolute
-31FC00224
-21FC00228
-11FC0022C
01FC00230
11FC00234
21FC00238
31FC0023C
400000000
51FC00240
600000004
71FC00244
800000000
91FC00248
NOP
0010
2.24 us
SRL t4,zero,t8
0010
3.00 us
NOP
0010
3.76 us
J 0X1FC084F0
0010
4.52 us
NOP
0010
5.24 us
LW v0,0x0000(s0)
0010
6.00 us
NOP
0010
6.76 us
STORE DATA 0xAAAA5555
0000
7.40 us
LW t1,0x0000(v0)
0010
7.88 us
STORE DATA 0x00000000
0000
8.52 us
NOP
0010
9.00 us
LOAD DATA 0xAAAA5555
0010
9.64 us
B 0x1FC00258
0010
10.32 us
Figure 6. Incorrectly Synchronized Capture (Note line -2)
210
USING THE IDT79R3051™ AND IDT79R3081™ WITH THE HP16500 LOGIC ANALYZER
APPLICATION NOTE AN-111
State/Timing E
Markers
Off
Label>
Base>
Listing 1
Invasm
Print
Run
ADDR
Hex
R3000 Mnemonic
hex
STAT
Hex
Time
Absolute
-41FC00220
-31FC00224
-21FC00228
-11FC0022C
01FC00230
11FC00234
21FC00238
31FC0023C
400000000
51FC00240
600000004
71FC00244
800000000
91FC00248
LW v0,0x0008(s0)
0010
2.24 us
NOP
0010
2.24 us
LOAD DATA 0x12620003
0010
3.00 us
NOP
0010
3.76 us
J 0X1FC084F0
0010
4.52 us
NOP
0010
5.24 us
LW v0,0x0000(s0)
0010
6.00 us
NOP
0010
6.76 us
STORE DATA 0xAAAA5555
0000
7.40 us
LW t1,0x0000(v0)
0010
7.88 us
STORE DATA 0x00000000
0000
8.52 us
NOP
0010
9.00 us
LOAD DATA 0xAAAA5555
0010
9.64 us
B 0x1FC00258
0010
10.32 us
Figure 7. Correctly Synchronized Capture (Note line -2)
ADDR(2)
RD
RD
x
ADDR(2)
x
0
0
1
1
0
1
0
1
1
0
0
0
NOTE: Signal will remain low while
not in a read cycle
00
01
00
01
TRIGGER needs to be double transition
to capture all four words
Figure 8. Simulated
RDCEN
signal
STORE
WR
If
∆y ≤
10ns, a Trigger Error will
occur (data will be diplayed), and
the STORE will be missed.
RDCEN
T.E
∆y
Figure 9.
RDCEN
Asserted during STORE
211
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