IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT
UNIVERSAL BUS
TRANSCEIVER WITH
3-STATE OUTPUTS
• 0.5 MICRON CMOS Technology
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range, or V
CC
= 2.7V to 3.6V, Extended
Range
• CMOS power levels (0.4µ W typ. static)
µ
• Rail-to-rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components
• Available in TSSOP package
IDT74FCT163601A
FEATURES:
DESCRIPTION:
The FCT163601/A 18-bit registered transceiver is built using advanced
dual metal CMOS technology. These 18-bit universal bus transceivers
combine D-type latches and D-type flip-flops to allow data flow in transpar-
ent, latched and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and
OEBA),
latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA)
inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA)
inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is high. When LEAB is low, the A data is
latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-
bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB.
Output enable
OEAB
is active low. When
OEAB
is low, the outputs are active.
When
OEAB
is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses
OEBA,
LEBA, CLKBA
and
CLKENBA.
The FCT163601 has series current limiting resistors. These offer low
ground bounce, minimal undershoot, and controlled output fall times-
reducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
1
56
55
2
28
30
29
27
A
1
3
CE
1D
C1
CLK
CE
1D
C1
CLK
54
B
1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-3251/6
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLKENAB
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLKBA
CLKENBA
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
–0.5 to +4.6
–0.5 to 7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +60
Unit
V
V
V
°C
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
V
TERM
(3)
Terminal Voltage with Respect to GND
V
TERM
(4)
Terminal Voltage with Respect to GND
T
STG
I
OUT
Storage Temperature
DC Output Current
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Outputs and I/O terminals.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
3.5
3.5
Max.
6
8
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(1,4)
CLKENAB
X
X
X
H
L
L
L
L
OEAB
H
L
L
L
L
L
L
L
Inputs
LEAB
X
H
H
L
L
L
L
L
CLKAB
X
X
X
X
↑
↑
TSSOP
TOP VIEW
L
H
A
X
L
H
X
L
H
X
X
Outputs
B
Z
L
H
B
0
(2)
L
H
B
0
(2)
B
0
(3)
PIN DESCRIPTION
Pin Names
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
Bx
CLKENAB
CLKENBA
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
A to B Clock Enable Input (Active LOW)
B to A Clock Enable Input (Active LOW)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA,
LEBA, CLKBA
and
CLKENBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑
= LOW-to-HIGH Transition
2
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 2.7V to 3.6V
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
V
IK
I
ODH
I
ODL
V
OH
Parameter
Input HIGH Level (Input pins)
Input HIGH Level (I/O pins)
Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
V
CC
= Min., I
IN
= –18mA
V
CC
= 3.3V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= 3.3V, V
IN
= V
IH
or V
IL,
V
O
= 1.5V
(3)
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
V
OL
Output LOW Voltage
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= 3V
V
IN
= V
IH
or V
IL
I
OS
V
H
I
CCL
I
CCH
I
CCZ
Short Circuit Current
(4)
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Max., V
O
= GND
(3)
—
–60
—
—
–135
150
0.1
–240
—
10
mA
mV
µA
I
OL
= 0.1mA
I
OL
= 16mA
I
OL
= 24mA
I
OL
= 24mA
—
—
—
—
—
0.2
0.3
0.3
0.2
0.4
0.55
0.5
V
I
OH
= –0.1mA
I
OH
= –3mA
I
OH
= –8mA
V
CC
= Max.
V
CC
= Max.
V
I
= 5.5V
V
I
= V
CC
V
I
= GND
V
I
= GND
V
O
= V
CC
V
O
= GND
Test Conditions
(1)
Guaranteed Logic HIGH Level
Min.
2
2
–0.5
—
—
—
—
—
—
—
–36
50
V
CC
-0.2
2.4
2.4
(5)
Typ.
(2)
—
—
—
—
—
—
—
—
—
–0.7
–60
90
—
3
3
Max.
5.5
V
CC
+0.5
0.8
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
V
V
mA
mA
µA
µA
V
Unit
V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. V
OH
= V
CC
–0.6V at rated current.
3
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply
Current TTL Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= V
CC
–0.6V
(3)
V
CC
= Max.
Outputs Open
OEAB
= V
CC
,
OEBA
= GND
One Input Toggling
50% Duty Cycle
V
CC
= Max., Outputs Open
f
CP
= 10MHz (CLKBA)
50% Duty Cycle
OEAB
= V
CC
,
OEBA
= GND
LEBA = GND
CLKENBA
= GND
f
i
= 5MHz
One Bit Toggling
V
CC
= Max., Outputs Open
f
CP
= 10MHz (CLKBA)
50% Duty Cycle
OEAB
= V
CC
,
OEBA
= GND
LEBA = GND
CLKENBA
= GND
f
i
= 2.5MHz
Eighteen Bits Toggling
V
IN
= V
CC
V
IN
= GND
Min.
—
—
Typ.
(2)
2
60
Max.
30
100
Unit
µA
µA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
—
0.6
1
mA
—
0.6
1
V
IN
= V
CC
V
IN
= GND
V
IN
= V
CC
–0.6V
V
IN
= GND
—
3
5
(5)
—
3
5.3
(5)
NOTES:
1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+ DI
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + fiNi)
I
CC
= Quiescent Current (I
CCL,
I
CCH
and I
CCZ
)
∆I
CC
= Power Supply Current for a TTL High Input
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at fi
4
IDT74FCT163601A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
SU
t
H
t
H
t
W
t
W
t
SK
(o)
Parameter
CLKAB or CLKBA frequency
(3)
Propagation Delay
Ax to Bx or Bx to Ax
Propagation Delay
LEBA to Ax, LEAB to Bx
Propagation Delay
CLKBA to Ax, CLKAB to Bx
Output Enable Time
OEBA
to Ax,
OEAB
to Bx
Output Disable Time
OEBA
to Ax,
OEAB
to Bx
Set-up Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
Set-up Time HIGH or LOW
Clock LOW
Ax to LEAB, Bx to LEBA
Clock HIGH
Set-up Time,
CLKEN
to CLK
Hold Time HIGH or LOW
Ax to LEAB, Bx to LEBA
Hold Time,
CLKEN
to CLK
LEAB or LEBA Pulse Width HIGH
CLKAB or CLKBA Pulse Width HIGH or LOW
Output Skew
(4)
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min.
(2)
—
1.5
1.5
1.5
1.5
1.5
3
0
2.5
2
2.5
1
0
2.5
3
—
Max.
150
5.5
6.2
6.3
6.5
5.2
—
—
—
—
—
—
—
—
—
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. This parameter is guaranteed but not tested.
4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
5
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