Traffic Manager Co-processor
Data Sheet
89TTM553
Preliminary Information*
Description
The 89TTM553 is a flow-based traffic management co-processor
that can be used in conjunction with the 89TTM552.
It has two major functional parts: the queue manager (QM) and the
FLQ scheduler. The QM is responsible for all the non-bandwidth func-
tions, which include managing up to 1 Million queuing structures,
handling cell and packet arrivals and departures from these queues, and
maintaining a database of congestion management and statistics
parameters for each flow queue (FLQ). The FLQ scheduler is respon-
sible for managing the FLQ bandwidth functions.
The 89TTM553 FLQ scheduler supports traffic scheduling on up to
1M discrete flows. In addition to the scheduling levels provided by the
89TTM552, the 89TTM553 provides one or two levels of additional
scheduling hierarchy. It also provides guaranteed minimum rate,
maximum rate capping, excess rate distribution using weighted fair
queuing (WFQ), byte rate shaping, and dynamic configuration adjust-
ments.
The 89TTM553 stores all the flow-based parameters (and state infor-
mation) that are made available to the 89TTM552 for flow-based
processing. When the 89TTM553 is used with the 89TTM552, conges-
tion and bandwidth management features are enabled at the flow level
as well as at the aggregate-flow level.
89TTM55x Features
Deterministic performance at 10 Gbps wire-speed (35 Mcps)
regardless of the number of flows, traffic size, and patterns.
◆
Up to 256 megabytes of external memory buffer space
(equivalent to a 210 ms buffer at 10 Gbps).
◆
Support (Rx and Tx) for industry-standard SPI-4 phase 2,
NPF Streaming Interface, and CSIX over LVDS.
◆
Hierarchical queuing and precise scheduling:
– Traffic management flexibility.
– Support for up to 4K aggregate flow queues (AFQs), 1K port
queues (PQs), 2K arrival reassembly queues (ARQs), and 1K
output queues/channels (OQs) with no external memory
required. Configurable AFQ-to-port assignments.
– Support for up to 1M discrete flows (FLQs), with queuing for
each flow, using external memory. Configurable mapping of
FLQs into aggregate flow queues.
– Two-level FLQ scheduling mode that supports up to 128K or
256K virtual pipe or subscriber queues with up to 8 or 4 CoS
priority queues each.
– Accurate byte-rate shaping at the FLQ, AFQ and port levels.
◆
Multiple levels of buffer congestion management.
– Hierarchical queue structure and thresholding.
– Congestion indication.
◆
– Dynamic adjustment of thresholds during periods of congestion.
– Packet discard (PD).
– Weighted random early discard (WRED).
– Local congestion indication (CI).
◆
Configurable forwarding based on classification index.
◆
Two ports for obtaining event-based statistics.
◆
Configurable on-chip diagnostic statistics.
◆
Bandwidth management rate guarantee and shaping
mechanisms for each flow, each aggregate flow and each
port queue.
– Priority and weighted bandwidth distribution mechanisms
across groups of flows and aggregate flows.
– Schedules rates as low as 2 kbps for each flow.
– One- and two-level byte-rate FLQ scheduling: maximum and
minimum rates, and strict priority and weighted fair queuing
(WFQ) for each FLQ. Per-flow byte-rate shaping.
– AFQ scheduling with byte-rate shaping: minimum and
maximum rates with VBR MBS and PCR enforcement. Excess
distribution using weighted fair queuing (WFQ) and PRR.
– Port queues: maximum rates with byte-rate scheduling.
◆
Wire-speed logical multicasting.
– Four classes of service.
– Programmable service rate (minimum and excess bandwidth
distribution).
– Programmable thresholds.
– Branch connections can be added and deleted during live
traffic.
– Traffic management features on all multicast roots and
branches.
◆
Multicast label generation for spatial multicast support.
◆
Integrated wire-speed AAL-5 segmentation and reassembly
(AAL-5 CPCS SAR) in the datapath.
◆
32-bit processor interface running at up to 66 MHz with
integrated AAL-5 SAR and DMA engine for data insertion and
extraction.
– Four classes of service.
– Integrated AAL-5-compliant and packet-based SAR.
– Programmable service rate.
– Programmable queue thresholds.
– Use of descriptors and DMA support for maximum perfor-
mance.
– 16-bit data bus transfer at up to 66 MHz.
◆
Algorithms implemented in hardware; software intervention
required for initialization and configuration only.
◆
Error protection on all external RAM and BIST on all internal
RAM.
◆
Inter-operable with the IDT ZTM200 traffic manager.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 29
©
2004 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
January 12, 2005
DSC 6797
IDT 89TTM553
89TTM55x Functional Block Diagram
Data Buffer Memory (DDR SDRAM)
89TTM552
Multicast
Engine (DFC)
SPI-4.2
or
Streaming
Interface
or
SIX-over-LVDS
Control Path SAR
(SAR)
CPU and Peripheral
Interface (CPIF, DMA)
ZBus
Rx
DSR,
BRX
Memory Controller
(PBC)
OQ Manager
(VOQM, BPQ)
Datapath
AAL-5
SAR (ILS)
Tx
DST,
BTX
SPI-4.2
or
Streaming
Interface
or
CSIX-over-LVD
Forwarding
and
Thresholding
Engine (AC)
Queue Manager
(QM)
Packet
Scheduler
(SS)
Statistics
Processor
(SP)
External
Statistics
Port
Extended Scheduler
Interface
89TTM553
89TTM552-to-89TTM553
Interface
Statistics
Processor
(SP)
Packet
Scheduler
(ARS, GS,
WFQ)
Forwarding
and
Thresholding
Engine (AC)
Queue Manager
(QM)
CPU and Peripheral
Interface (CPIF, DMA)
ZBus
2 of 29
*Notice: The information in this document is subject to change without notice
January 12, 2005
IDT 89TTM553
89TTM553 Pin Description
Note:
Information in this section is subject to change. Contact your IDT FAE before making design decisions.
In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bi-directional, and P for power.
Signal Name
BLL_CLK_CP,
BLL_CLK_CN
I/O Type
1.5V HSTL Class 1
Dir.
I
Freq.
175 MHz
Remarks
BLL QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
BLL QDR SRAM output clock: This clock pair times the control
outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
BLL QDR SRAM address outputs.
BLL QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
BLL QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations
BLL QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
BLL QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations
HSTL reference. Nominally V
DDQ
/ 2, so connect to 0.75 V
BLL_CLK_KP,
BLL_CLK_KN
BLL_ADDR[21:0]
BLL_RD_N
1.5V HSTL Class 1
O
175 MHz
1.5V HSTL Class 1
1.5V HSTL Class 1
O
O
175 MHz
175 MHz
BLL_DIN[17:0]
1.5V HSTL Class 1
I
175 MHz
BLL_WR_N
1.5V HSTL Class 1
O
175 MHz
BLL_DOUT[17:0]
BLL_VREF
1.5V HSTL Class 1
0.75V
O
—
175 MHz
—
Table 1 Buffer Linked List QDR SRAM
Signal Name
BXT_CLK_CP,
BXT_CLK_CN
I/O Type
1.5V HSTL Class 1
Dir.
I
Freq.
175 MHz
Remarks
BXT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
BXT QDR SRAM output clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
BXT QDR SRAM address outputs.
BXT QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
BXT QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations
BXT_CLK_KP,
BXT_CLK_KN
BXT_ADDR[21:0]
BXT_RD_N
1.5V HSTL Class 1
O
175 MHz
1.5V HSTL Class 1
1.5V HSTL Class 1
O
O
175 MHz
175 MHz
BXT_DIN[3:0]
1.5V HSTL Class 1
I
175 MHz
Table 2 Buffer Linked List Extension QDR SRAM (Part 1 of 2)
3 of 29
*Notice: The information in this document is subject to change without notice
January 12, 2005
IDT 89TTM553
Signal Name
BXT_WR_N
I/O Type
1.5V HSTL Class 1
Dir.
O
Freq.
175 MHz
Remarks
BXT QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
BXT QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations
HSTL reference. Nominally V
DDQ
/ 2, so connect to 0.75 V
BXT_DOUT[3:0]
BXT_LLT_VREF
1.5V HSTL Class 1
0.75V
O
—
175 MHz
—
Table 2 Buffer Linked List Extension QDR SRAM (Part 2 of 2)
Signal Name
FCT_CLK_CP,
FCT_CLK_CN
I/O Type
1.5V HSTL Class 1
Dir.
I
Freq.
175 MHz
Remarks
FCT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
FCT QDR SRAM output clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
FCT QDR SRAM address outputs.
FCT QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
FCT QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations
FCT QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
FCT QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations
HSTL reference. Nominally V
DDQ
/ 2, so connect to 0.75 V
FCT_CLK_KP,
FCT_CLK_KN
FCT_ADDR[19:0]
FCT_RD_N
1.5V HSTL Class 1
O
175 MHz
1.5V HSTL Class 1
1.5V HSTL Class 1
O
O
175 MHz
175 MHz
FCT_DIN[27:0]
1.5V HSTL Class 1
I
175 MHz
FCT_WR_N
1.5V HSTL Class 1
O
175 MHz
FCT_DOUT[27:0]
FCT_VREF[1:0]
1.5V HSTL Class 1
0.75
O
—
175 MHz
—
Table 3 Flow Control Table QDR SRAM
Signal Name
FPT_CLK_CP,
FPT_CLK_CN
I/O Type
1.5V HSTL Class 1
Dir.
I
Freq.
175 MHz
Remarks
FPT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
FPT QDR SRAM output clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
FPT QDR SRAM address outputs.
FPT QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
FPT_CLK_KP,
FPT_CLK_KN
FPT_ADDR[20:0]
FPT_RD_N
1.5V HSTL Class 1
O
175 MHz
1.5V HSTL Class 1
1.5V HSTL Class 1
O
O
175 MHz
175 MHz
Table 4 Flow Parameters Table QDR SRAM (Part 1 of 2)
4 of 29
*Notice: The information in this document is subject to change without notice
January 12, 2005
IDT 89TTM553
Signal Name
FPT_DIN[35:0]
I/O Type
1.5V HSTL Class 1
Dir.
I
Freq.
175 MHz
Remarks
FPT QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations
FPT QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
FPT QDR SRAM synchronous write byte enables (active low)
FPT QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations
HSTL reference. Nominally V
DDQ
/ 2, so connect to 0.75 V
FPT_WR_N
1.5V HSTL Class 1
O
175 MHz
FPT_BW_N[3:0]
FPT_DOUT[35:0]
FPT_VREF[1:0]
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75V
O
O
—
175 MHz
175 MHz
—
Table 4 Flow Parameters Table QDR SRAM (Part 2 of 2)
Signal Name
GPT_CLK_CP,
GPT_CLK_CN
I/O Type
1.5V HSTL Class 1
Dir.
I
Freq.
175 MHz
Remarks
GPT QDR SRAM input clock: This clock pair registers data
inputs on the rising edge of C and C#. All synchronous inputs
must meet setup and hold times around the clock rising
edges.
GPT QDR SRAM output clock: This clock pair times the con-
trol outputs to the rising edge of K, and times the address and
data outputs to the rising edge of K and K#.
GPT QDR SRAM address outputs.
GPT QDR SRAM synchronous read output (active low): When
asserted, a read cycle is initiated to the external QDR SRAM
devices.
GPT QDR SRAM data inputs: Input data must meet setup and
hold times around the rising edges of C and C# during read
operations.
GPT QDR SRAM synchronous write output (active low): When
asserted, a write cycle is initiated to the external QDR SRAM
devices.
GPT QDR SRAM synchronous byte enables (active low).
GPT QDR SRAM write data outputs: Output data is synchro-
nized to the K and K# during write operations.
HSTL reference. Nominally V
DDQ
/ 2, so connect to 0.75 V
GPT_CLK_KP,
GPT_CLK_KN
GPT_ADDR[20:0]
GPT_RD_N
1.5V HSTL Class 1
O
175 MHz
1.5V HSTL Class 1
1.5V HSTL Class 1
O
O
175 MHz
175 MHz
GPT_DIN[17:0]
1.5V HSTL Class 1
I
175 MHz
GPT_WR_N
1.5V HSTL Class 1
O
175 MHz
GPT_BW_N[1:0]
GPT_DOUT[17:0]
GPT_VREF
1.5V HSTL Class 1
1.5V HSTL Class 1
0.75V
O
O
—
175 MHz
175 MHz
—
Table 5 Group Parameters Table QDR SRAM
5 of 29
*Notice: The information in this document is subject to change without notice
January 12, 2005
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
