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89HPES4T4ZABC: 产品描述PCI Bus Controller, PBGA144, 13 X 13 MM, 1 MM PITCH, CABGA-144; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小233KB，共23页; 制造商IDT (Integrated Device Technology)

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89HPES4T4ZABC概述

PCI Bus Controller, PBGA144, 13 X 13 MM, 1 MM PITCH, CABGA-144

89HPES4T4ZABC规格参数

参数名称	属性值
是否无铅	含铅
是否Rohs认证	不符合
厂商名称	IDT (Integrated Device Technology)
零件包装代码	BGA
包装说明	LBGA,
针数	144
Reach Compliance Code	not_compliant
ECCN代码	3A001.A.3
地址总线宽度
总线兼容性	PCI
最大时钟频率	125 MHz
驱动器接口标准	IEEE 1149.1
外部数据总线宽度
JESD-30 代码	S-PBGA-B144
JESD-609代码	e0
长度	13 mm
湿度敏感等级	3
端子数量	144
最高工作温度	70 °C
最低工作温度
封装主体材料	PLASTIC/EPOXY
封装代码	LBGA
封装形状	SQUARE
封装形式	GRID ARRAY, LOW PROFILE
峰值回流温度（摄氏度）	225
认证状态	Not Qualified
座面最大高度	1.5 mm
最大供电电压	1.1 V
最小供电电压	0.9 V
标称供电电压	1 V
表面贴装	YES
技术	CMOS
温度等级	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)
端子形式	BALL
端子节距	1 mm
端子位置	BOTTOM
处于峰值回流温度下的最长时间	20
宽度	13 mm
uPs/uCs/外围集成电路类型	BUS CONTROLLER, PCI

89HPES4T4ZABC文档预览

4-Lane 4-Port

PCI Express® Switch

89HPES4T4

Data Sheet

Advance Information*

Device Overview

◆

The 89HPES4T4 is a member of IDT’s PRECISE™ family of PCI

Express switching solutions. The PES4T4 is a 4-lane, 4-port peripheral

chip that performs PCI Express Base switching. It provides connectivity

and switching functions between a PCI Express upstream port and up to

four downstream ports and supports switching between downstream

ports.

◆

Features

◆

High Performance PCI Express Switch

– Four 2.5 Gbps PCI Express lanes

– Four switch ports

– x1 Upstream port

– Three x1 Downstream ports

– Low latency cut-through switch architecture

– Support for Max payload sizes up to 256 bytes

– One virtual channel

– Eight traffic classes

– PCI Express Base Specification Revision 1.1 compliant

Flexible Architecture with Numerous Configuration Options

– Automatic lane reversal on all ports

– Automatic polarity inversion on all lanes

– Ability to load device configuration from serial EEPROM

Legacy Support

– PCI compatible INTx emulation

– Bus locking

◆

Highly Integrated Solution

– Requires no external components

– Incorporates on-chip internal memory for packet buffering and

queueing

– Integrates four 2.5 Gbps embedded SerDes with 8B/10B

encoder/decoder (no separate transceivers needed)

Reliability, Availability, and Serviceability (RAS) Features

– Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

– Supports ECRC and Advanced Error Reporting

– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O

– Compatible with Hot-Plug I/O expanders used on PC mother-

boards

Power Management

– Utilizes advanced low-power design techniques to achieve low

typical power consumption

– Supports PCI Power Management Interface specification (PCI-

PM 1.2)

– Unused SerDes are disabled.

– Supports Advanced Configuration and Power Interface Speci-

fication, Revision 2.0 (ACPI) supporting active link state

Testability and Debug Features

– Built in Pseudo-Random Bit Stream (PRBS) generator

– Numerous SerDes test modes

– Ability to bypass link training and force any link into any mode

– Provides statistics and performance counters

Block Diagram

4-Port Switch Core / 4 PCI Express Lanes

Frame Buffer

Route Table

Port

Arbitration

Scheduler

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Mux / Demux

Phy

Logical

Layer

Mux / Demux

Phy

Logical

Layer

Mux / Demux

Phy

Logical

Layer

Mux / Demux

Phy

Logical

Layer

SerDes

(Port 0)

(Port 2)

(Port 3)

(Port 4)

Figure 1 Internal Block Diagram

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 23

2007 Integrated Device Technology, Inc.

*Notice: The information in this document is subject to change without notice

September 7, 2007

Advance Information

IDT 89HPES4T4 Data Sheet

◆

5 General Purpose Input/Output Pins

– Each pin may be individually configured as an input or output

– Each pin may be individually configured as an interrupt input

– Each pin has a selectable alternate function

Packaged in a 13mm x 13mm 144-ball BGA with 1mm ball spacing

Product Description

Utilizing standard PCI Express interconnect, the PES4T4 provides the most efficient fan-out solution for applications requiring x1 connectivity, low

latency, and simple board layout with a minimum number of board layers. Each lane provides 2.5 Gbps of bandwidth in both directions and is fully

compliant with PCI Express Base specification 1.1.

The PES4T4 is based on a flexible and efficient layered architecture. The PCI Express layer consists of SerDes, Physical, Data Link and Transac-

tion layers in compliance with PCI Express Base specification Revision 1.1. The PES4T4 can operate either as a store and forward or cut-through

switch and is designed to switch memory and I/O transactions. It supports eight Traffic Classes (TCs) and one Virtual Channel (VC) with sophisticated

resource management to allow efficient switching for applications requiring additional narrow port connectivity and also some high-end connectivity.

Processor

North

Bridge

Memory

South

Bridge

PES4T4

LOM

1394

Figure 2 I/O Expansion Application

SMBus Interface

The PES4T4 contains an SMBus master interface. This master interface allows the default configuration register values of the PES4T4 to be over-

ridden following a reset with values programmed in an external serial EEPROM. The master interface is also used by an external Hot-Plug I/O

expander. Two pins make up the SMBus master interface. These pins consist of an SMBus clock pin and an SMBus data pin.

Hot-Plug Interface

The PES4T4 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the PES4T4 utilizes

an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset and configuration, when-

ever the state of a Hot-Plug output needs to be modified, the PES4T4 generates an SMBus transaction to the I/O expander with the new value of all of

the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on the IOEXPINTN input pin (alternate

function of GPIO) of the PES4T4. In response to an I/O expander interrupt, the PES4T4 generates an SMBus transaction to read the state of all of the

Hot-Plug inputs from the I/O expander.

2 of 23

September 7, 2007

Advance Information

IDT 89HPES4T4 Data Sheet

General Purpose Input/Output

The PES4T4 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may

be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alter-

nate functions may be enabled via software or serial configuration EEPROM.

Pin Description

The following tables lists the functions of the pins provided on the PES4T4. Some of the functions listed may be multiplexed onto the same pin. The

active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.

All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal

PE0RP[0]

PE0RN[0]

PE0TP[0]

PE0TN[0]

PE2RP[0]

PE2RN[0]

PE2TP[0]

PE2TN[0]

PE3RP[0]

PE3RN[0]

PE3TP[0]

PE3TN[0]

PE4RP[0]

PE4RN[0]

PE4TP[0]

PE4TN[0]

PEREFCLKP

PEREFCLKN

Type

Name/Description

PCI Express Port 0 Serial Data Receive.

Differential PCI Express receive

pair for port 0.

PCI Express Port 0 Serial Data Transmit.

Differential PCI Express trans-

mit pair for port 0.

PCI Express Port 2 Serial Data Transmit.

Differential PCI Express trans-

mit pair for port 2.

PCI Express Port 3 Serial Data Receive.

Differential PCI Express receive

pair for port 3.

PCI Express Port 3 Serial Data Transmit.

Differential PCI Express trans-

mit pair for port 3.

PCI Express Port 4 Serial Data Receive.

Differential PCI Express receive

pair for port 4.

PCI Express Port 4 Serial Data Transmit.

Differential PCI Express trans-

mit pair for port 4.

PCI Express Reference Clock.

Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes.

Table 1 PCI Express Interface Pins

Signal

MSMBCLK

MSMBDAT

Type

I/O

Name/Description

Master SMBus Clock.

This bidirectional signal is used to synchronize

transfers on the master SMBus.

Master SMBus Data.

This bidirectional signal is used for data on the mas-

ter SMBus.

Table 2 SMBus Interface Pins

3 of 23

September 7, 2007

Advance Information

PCI Express Port 2 Serial Data Receive.

Differential PCI Express receive

pair for port 2.

IDT 89HPES4T4 Data Sheet

Signal

GPIO[0]

Type

I/O

Name/Description

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P2RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 2

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P4RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 4

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: IOEXPINTN0

Alternate function pin type: Input

Alternate function: I/O Expander interrupt 0 input

GPIO[1]

I/O

GPIO[2]

I/O

GPIO[9]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: P3RSTN

Alternate function pin type: Output

Alternate function: Reset output for downstream port 3

Table 3 General Purpose I/O Pins

Signal

APWRDISN

CCLKDS

Type

Name/Description

Auxiliary Power Disable Input.

When this pin is active, it disables the

device from using auxiliary power supply.

Common Clock Downstream.

The assertion of this pin indicates that all

downstream ports are using the same clock source as that provided to

downstream devices.This bit is used as the initial value of the Slot Clock

Configuration bit in all of the Link Status Registers for downstream ports.

The value may be override by modifying the SCLK bit in the downstream

port’s PCIELSTS register.

Common Clock Upstream.

The assertion of this pin indicates that the

upstream port is using the same clock source as the upstream device. This

bit is used as the initial value of the Slot Clock Configuration bit in the Link

Status Register for the upstream port. The value may be overridden by

modifying the SCLK bit in the PA_PCIELSTS register.

Fundamental Reset.

Assertion of this signal resets all logic inside the

PES4T4 and initiates a PCI Express fundamental reset.

Table 4 System Pins (Part 1 of 2)

CCLKUS

PERSTN

4 of 23

September 7, 2007

Advance Information

GPIO[7]

I/O

General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

Alternate function pin name: GPEN

Alternate function pin type: Output

Alternate function: General Purpose Event (GPE) output

IDT 89HPES4T4 Data Sheet

Signal

RSTHALT

Type

Name/Description

Reset Halt.

When this signal is asserted during a PCI Express fundamental

reset, the PES4T4 executes the reset procedure and remains in a reset

state with the Master SMBus active. This allows software to read and write

registers internal to the device before normal device operation begins. The

device exits the reset state when the RSTHALT bit is cleared in the

PA_SWCTL register by the SMBus master.

Switch Mode.

These configuration pins determine the PES4T4 switch

operating mode.

0x0 - Normal switch mode

0x1 - Normal switch mode with Serial EEPROM initialization

0x2 - through 0xF Reserved

Wake Input/Output.

The WAKEN signal is an input or output. The WAKEN

signal input/output selection can be made through WAKEDIR bit setting in

the WAKEUPCNTL register.

Table 4 System Pins (Part 2 of 2)

SWMODE[2:0]

WAKEN

I/O

Signal

JTAG_TCK

Type

Name/Description

JTAG Clock.

This is an input test clock used to clock the shifting of data

into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is

independent of the system clock with a nominal 50% duty cycle.

JTAG Data Input.

This is the serial data input to the boundary scan logic or

JTAG Controller.

JTAG Data Output.

This is the serial data shifted out from the boundary

scan logic or JTAG Controller. When no data is being shifted out, this signal

is tri-stated.

JTAG Mode.

The value on this signal controls the test mode select of the

boundary scan logic or JTAG Controller.

JTAG Reset.

This active low signal asynchronously resets the boundary

scan logic and JTAG TAP Controller. An external pull-up on the board is

recommended to meet the JTAG specification in cases where the tester

can access this signal. However, for systems running in functional mode,

one of the following should occur:

1) actively drive this signal low with control logic

2) statically drive this signal low with an external pull-down on the board

Table 5 Test Pins

JTAG_TDI

JTAG_TDO

JTAG_TMS

JTAG_TRST_N

Signal

CORE

I/O

APE

Type

Name/Description

Core VDD.

Power supply for core logic.

I/O VDD.

LVTTL I/O buffer power supply.

PCI Express Digital Power.

PCI Express digital power used by the digital

power of the SerDes.

PCI Express Analog Power.

PCI Express analog power used by the PLL

and bias generator.

PCI Express Termination Power.

Ground.

Table 6 Power and Ground Pins

5 of 23

September 7, 2007

Advance Information

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89HPES4T4ZABC

89HPES4T4ZABC概述

89HPES4T4ZABC规格参数

89HPES4T4ZABC文档预览

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