W124
100-MHz Spread Spectrum Motherboard Frequency Generator
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Reduces measured EMI by as much as 10 dB
• I
2
C-programmable
• Two skew-controlled copies of CPU output
• Seven copies of PCI output (synchronous with CPU
output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz output is determined by resistor
straps on power-up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Programmable to 133, 124, 112, 103, 100 MHz, and below
• For three DIMM designs, see also the W40S11-23 buffer
chip, and for four DIMM designs see the W40S12-24 or
W40S01-04 chips
Table 1. Pin Selectable Frequency
SEL100/66#
1
0
CPU(0:1)
100 MHz
66.8 MHz
PCI
33.3 MHz
33.4 MHz
Block Diagram
VDDQ3
REF2X/SEL48#
X1
X2
XTAL
OSC
PLL Ref Freq
VDDQ2
IOAPIC
Pin Configuration
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
GND
SDATA
SCLOCK
SEL100/66#
GND
VDDQ2
CPU0
CPU1
SEL100/66#
PLL 1
÷2/÷3
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
SDATA
SCLOCK
I
2
C
LOGIC
PCI5
PCI6
VDDQ3
PLL2
÷1/÷2
24/48MHz
48MHz
Cypress Semiconductor Corporation
Document #: 38-07315 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 11, 2002
W124
Pin Definitions
Pin Name
CPU0:1
PCI1:6
PCI_F
IOAPIC
48MHz
24/48MHz
REF2X/SEL48#
Pin No.
22, 21
5, 6, 7, 8, 10,
11, 4
24
13
14
27
Pin Type
O
O
Pin Description
CPU Clock Outputs 0 through 1:
These two CPU clocks run at a frequency set
by SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.
PCI Clock Outputs 1 through 6 and PCI_F:
These seven PCI clock outputs run
synchronously to the CPU clock. Voltage swing is set by the power connection
to VDDQ3.
I/O APIC Clock Output:
Provides 14.318-MHz fixed frequency. The output
voltage swing is set by the power connection to VDDQ2.
48-MHz Output:
Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24-MHz or 48-MHz Output:
Frequency is set by the state of pin 27 on power-up.
I/O Dual Function REF2X and SEL48# pin:
Upon power-up, the state of
SEL48# is latched. The initial state is set by either a 10K resistor to GND or to
VDD. A 10K resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped
to VDD, pin 14 will output 24 MHz. After 2 ms, the pin becomes a high-drive
output that produces a copy of 14.318 MHz.
Frequency Selection Input:
Selects CPU clock frequency as shown in
Table 1.
I
2
C Data Pin:
Data should be presented to this input as described in the I
2
C
section of this data sheet. Internal 250 KΩ pull-up resistor.
I
2
C Clock Pin:
The I
2
C Data clock should be presented to this input as described
in the I
2
C section of this data sheet.
Crystal Connection or External Reference Frequency Input:
Connect to
either a 14.318-MHz crystal or other reference signal.
Crystal Connection:
An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
Power Connection:
Power supply for PCI output buffers, 48-MHz USB output
buffers, Reference output buffer, core logic and PLL circuitry. Connect to 3.3V
supply.
Power Connection:
Power supply for IOAPIC and CPU output buffers. Connect
to 2.5V supply.
Ground Connections:
Connect all ground pins to the common system ground
plane.
O
O
O
I/O
SEL100/66#
SDATA
SCLOCK
X1
X2
VDDQ3
16
18
17
1
2
9,12,20,26
I
I/O
I
I
I
P
VDDQ2
GND
23, 25
3, 15, 19, 28
P
G
Document #: 38-07315 Rev. **
Page 2 of 13
W124
Overview
The W124, a motherboard clock synthesizer, can provide
either a 2.5V or 3.3V CPU clock swing, making it suitable for
a variety of CPU options. A fixed 48-MHz clock is provided for
other system functions. The W124 supports spread spectrum
clocking for reduced EMI.
output buffer is three-stated, allowing the output strapping
resistor on the l/O pin to pull the pin and its associated capac-
itive clock load to either a logic HIGH or LOW state. At the end
of the 2-ms period, the established logic “0” or “1” condition of
the l/O pin is then latched. Next the output buffer is enabled,
which converts the l/O pin into an operating clock output. The
2-ms timer starts when V
DD
reaches 2.0V. The input bit can
only be reset by turning V
DD
off and then back on again.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
a clock output is 25Ω (nominal), which is minimally affected by
the 10-kΩ strap to ground or V
DD
. As with the series termi-
nation resistor, the output strapping resistor should be placed
as close to the l/O pin as possible in order to keep the inter-
connecting trace short. The trace from the resistor to ground
or V
DD
should be kept less than two inches in length to prevent
system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input
period, a 14.318-MHz output frequency is delivered on the pin,
assuming that V
DD
has stabilized. If V
DD
has not yet reached
full value, output frequency initially may be below target but will
increase to target once V
DD
voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
V
DD
Output Strapping Resistor
10 kΩ
(Load Option 1)
W124
Output
Buffer
Power-on
Reset
Timer
Output Three-state
Control
Functional Description
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with
input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or V
DD
. Connection to ground sets a
latch to “0,” connection to V
DD
sets a latch to “1.”
Figure 1
and
Figure 2
show two suggested methods for strapping resistor
connections.
Upon W124 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the Reference clock
Series Termination Resistor
R
Clock Load
Hold
Output
Low
D
10 kΩ
(Load Option 0)
Logic
Q
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
V
DD
10 kΩ
W124
Output
Buffer
Power-on
Reset
Timer
Output Three-state
Control
Output Strapping Resistor
Series Termination Resistor
R
Clock Load
Hold
Output
Low
D
Resistor Value R
Logic
Q
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Document #: 38-07315 Rev. **
Page 3 of 13
W124
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the
amplitudes of the radiated electromagnetic emissions are
reduced. This effect is depicted in
Figure 3.
As shown in
Figure 3,
a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log
10
(P) + 9*log
10
(F)
where
P
is the percentage of deviation and
F
is the frequency
in MHz where the reduction is measured.
The output clock is modulated with a waveform depicted in
Figure 4.
This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is ±0.5% of the center
frequency.
Figure 4
details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
Spread Spectrum clocking is activated or deactivated by
selecting the appropriate values for bits 1–0 in data byte 0 of
the I
2
C data stream. Refer to
Table 5
for more details.
Figure 3. Clock Harmonic With and Without SSCG Modulation Frequency Domain Representation
MAX (+0.5%)
FREQUENCY
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
10%
20%
30%
40%
50%
60%
70%
80%
90%
MIN (–0.5%)
Figure 4. Typical Modulation Profile
Document #: 38-07315 Rev. **
Page 4 of 13
100%
W124
Serial Data Interface
The W124 features a two-pin, serial data interface that can be
used to configure internal register settings that control
particular device functions. Upon power-up, the W124
initializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is write-
only (to the clock chip) and is the dedicated function of device
pins SDATA and SCLOCK. In motherboard applications,
SDATA and SCLOCK are typically driven by two logic outputs
Table 2. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
Description
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Provides CPU/PCI frequency selections beyond the
100- and 66.66-MHz selections that are provided by
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.
All clock outputs toggle in relation to X1 input,
internal PLL is bypassed. Refer to
Table 4.
Reserved function for future device revision or
production device testing.
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change under
normal system operation.
Production PCB testing.
No user application. Register bit must be
written as 0.
of the chipset. Clock device register changes are normally
made upon system initialization, if required. The interface can
also be used during system operation for power management
functions.
Table 2
summarizes the control functions of the
serial data interface.
Operation
Data is written to the W124 in ten bytes of eight bits each.
Bytes are written in the order shown in
Table 3.
CPU Clock Frequency
Selection
Output Three-state
Test Mode
(Reserved)
Puts all clock outputs into a high-impedance state. Production PCB testing.
Table 3. Byte Writing Sequence
Byte Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
Byte Description
Commands the W124 to accept the bits in data bytes 3–6 for internal
register configuration. Since other devices may exist on the same
common serial data bus, it is necessary to have a specific slave address
for each potential receiver. The slave receiver address for the W124 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W124, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another
addressed slave receiver on the serial data bus.
Unused by the W124, therefore bit values are ignored (don’t care). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communi-
cation protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
Refer to Cypress SDRAM drivers (W40S11-23, W40S12-24,
W40S01-04H).
2
Command
Code
Don’t Care
3
Byte Count
Don’t Care
4
5
6
7
8
9
10
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Don’t Care
Refer to
Table 4
The data bits in these bytes set internal W124 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to
Table 4,
Data Byte Serial Configuration Map.
Document #: 38-07315 Rev. **
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