MB9B100A Series
32-bit ARM
®
Cortex
®
-M3
FM3 Microcontroller
The MB9B100A Series are a highly integrated 32-bit microcontroller that target for high-performance and cost-sensitive embedded
control applications.
®
®
The MB9B100A Series are based on the ARM Cortex -M3 Processor and on-chip Flash memory and SRAM, and peripheral
2
functions, including Motor Control Timers, ADCs and Communication Interfaces (UART, CSIO, I C, LIN).
The products which are described in this data sheet are placed into TYPE0 product categories in "FM3 Family PERIPHERAL
MANUAL".
Features
32-bit ARM Cortex -M3 Core
Processor version: r2p0
Up to 80MHz Frequency Operation
Memory Protection Unit (MPU): improve the reliability of an
embedded system
®
®
Multi-function Serial Interface (Max. 8channels)
4 channels with 16steps × 9bit FIFO (ch.4-ch.7), 4 channels
without FIFO (ch.0-ch.3)
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
I C
Integrated Nested Vectored Interrupt Controller (NVIC): 1
NMI (non-maskable interrupt) and 48 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
[UART]
Full-duplex double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
On-chip Memories
[Flash memory]
Up to 512 Kbyte
Read cycle: 0wait-cycle@up to 60MHz, 2wait-cycle* above
*: Instruction pre-fetch buffer is included. So when CPU
access continuously, it becomes 0wait-cycle
Security function for code protection
[SRAM]
This series contain a total of up to 64Kbyte on-chip SRAM. This
is composed of two independent SRAM(SRAM0, SRAM1).
SRAM0 is connected to I-code bus and D-code bus of
Cortex-M3 core. SRAM1 is connected to System bus.
Various error detect functions available (parity errors, framing
errors, and overrun errors)
[CSIO]
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
[LIN]
LIN protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generate (can be changed 13-16bit length)
LIN break delimiter generate (can be changed 1-4bit length)
Various error detect functions available (parity errors, framing
errors, and overrun errors)
SRAM0: Up to 32 Kbyte
SRAM1: Up to 32 Kbyte
Cypress Semiconductor Corporation
Document Number: 002-05605 Rev.*A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 14, 2016
MB9B100A Series
[I C]
Standard-mode (Max.100kbps) / Fast-mode (Max.400Kbps)
supported
2
Multi-function Timer (Max. 2units)
The Multi-function timer is composed of the following blocks.
16-bit free-run timer × 3ch/unit
Input capture × 4ch/unit
Output compare × 6ch/unit
A/D activation compare × 3ch/unit
Waveform generator × 3ch/unit
16-bit PPG timer × 3ch/unit
The following function can be used to achieve the motor
control.
External Bus Interface
Supports SRAM, NOR& NAND Flash device
Up to 8 chip selects
8/16-bit Data width
Up to 25-bit Address bit
Maximum area size : Up to 256 Mbytes
DMA Controller (8channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Quadrature Position/Revolution Counter (QPRC)
(Max. 2units)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32bit(4Gbyte)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
A/D Converter (Max. 16channels)
[12-bit A/D Converter]
Successive Approximation Register type
Built-in 3unit
Conversion time: 1.0μs@5V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4steps)
The detection edge of the three external event input pins AIN,
BIN and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Dual Timer (Two 32/16bit Down Counter)
The Dual Timer consists of two programmable 32/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from sleep mode.
Base Timer (Max. 8channels)
Operation mode is selectable from the followings for each
channel.
16-bit PWM timer
16-bit PPG timer
16/32-bit reload timer
16/32-bit PWC timer
Interval timer: up to 64s (Max.)@ Sub Clock : 32.768kHz
Document Number: 002-05605 Rev.*A
Page 2 of 105
MB9B100A Series
Watch dog Timer (2channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by the built-in low-speed
CR oscillator. Therefore,”Hardware" watchdog is active in any
low-power consumption modes except STOP mode.
Clock Super Visor (CSV)
Clocks generated by CR oscillators are used to supervise
abnormality of the external clocks.
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
External Interrupt Controller Unit
Up to 16 external vectors
Include one non-maskable interrupt (NMI)
General Purpose I/O Port
This series can use its pins as general-purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated.
Low Voltage Detector (LVD)
This series include 2-stage monitoring of voltage on the VCC.
When the voltage falls below the voltage has been set, Low
Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Three low-power consumption modes supported.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 100 high-speed general-purpose I/O Ports@120pin
Package
SLEEP
TIMER
STOP
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Embedded Trace Macrocells (ETM) provide comprehensive
debug and trace facilities.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Power Supply
VCC
= 2.7 V to 5.5 V: Correspond to the wide range
voltage.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and Main PLL) that
are dynamically selectable.
Main Clock
Sub Clock
Built-in high-speed CR Clock
Built-in low-speed CR Clock
Main PLL Clock
[Resets]
Reset requests from INITX pins
Power-on reset
Software reset
Watchdog timers reset
Low-voltage detector reset
Clock supervisor reset
Document Number: 002-05605 Rev.*A
: 4 MHz to 48 MHz
: 32.768 kHz
: 4 MHz
: 100 kHz
Page 3 of 105
MB9B100A Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Packages ........................................................................................................................................................................... 7
3. Pin Assignment ................................................................................................................................................................. 8
4. List of Pin Functions....................................................................................................................................................... 11
5. I/O Circuit Type................................................................................................................................................................ 39
6. Handling Precautions ..................................................................................................................................................... 43
6.1
Precautions for Product Design ................................................................................................................................... 43
6.2
Precautions for Package Mounting .............................................................................................................................. 44
6.3
Precautions for Use Environment ................................................................................................................................ 45
7. Handling Devices ............................................................................................................................................................ 46
8. Block Diagram ................................................................................................................................................................. 48
9. Memory Size .................................................................................................................................................................... 48
10. Memory Map .................................................................................................................................................................... 49
11. Pin Status in Each CPU State ........................................................................................................................................ 52
12. Electrical Characteristics ............................................................................................................................................... 57
12.1 Absolute Maximum Ratings ......................................................................................................................................... 57
12.2 Recommended Operating Conditions.......................................................................................................................... 59
12.3 DC Characteristics....................................................................................................................................................... 60
12.3.1 Current rating ............................................................................................................................................................... 60
12.3.2 Pin Characteristics ....................................................................................................................................................... 62
12.4 AC Characteristics ....................................................................................................................................................... 63
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 63
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 64
12.4.3 Built-in CR Oscillation Characteristics .......................................................................................................................... 64
12.4.4 Operating Conditions of Main PLL(In the case of using main clock for input of PLL) ................................................... 65
12.4.5 Operating Conditions of Main PLL(In the case of using built-in high speed CR) .......................................................... 65
12.4.6 Reset Input Characteristics .......................................................................................................................................... 66
12.4.7 Power-on Reset Timing................................................................................................................................................ 66
12.4.8 External Bus Timing ..................................................................................................................................................... 67
12.4.9 Base Timer Input Timing .............................................................................................................................................. 72
12.4.10 CSIO/UART Timing .................................................................................................................................................. 73
12.4.11 External input timing ................................................................................................................................................. 81
12.4.12 Quadrature Position/Revolution Counter timing ........................................................................................................ 82
2
12.4.13 I C timing .................................................................................................................................................................. 84
12.4.14 ETM timing ............................................................................................................................................................... 85
12.4.15 JTAG timing .............................................................................................................................................................. 86
12.5 12bit A/D Converter ..................................................................................................................................................... 87
12.6 Low-Voltage Detection Characteristics ........................................................................................................................ 90
12.6.1 Low-Voltage Detection Reset ....................................................................................................................................... 90
12.6.2 Interrupt of Low-Voltage Detection ............................................................................................................................... 90
12.7 Flash Memory Write/Erase Characteristics ................................................................................................................. 91
12.7.1 Write / Erase time......................................................................................................................................................... 91
12.7.2 Erase/write cycles and data hold time .......................................................................................................................... 91
12.8 Return Time from Low-Power Consumption Mode ...................................................................................................... 92
12.8.1 Return Factor: Interrupt ................................................................................................................................................ 92
12.8.2 Return Factor: Reset .................................................................................................................................................... 94
Document Number: 002-05605 Rev.*A
Page 4 of 105
MB9B100A Series
13. Example of Characteristic .............................................................................................................................................. 96
14. Ordering Information ...................................................................................................................................................... 98
15. Package Dimensions ...................................................................................................................................................... 99
16. Major Changes .............................................................................................................................................................. 102
Document History ............................................................................................................................................................... 104
Document Number: 002-05605 Rev.*A
Page 5 of 105
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