®
Includes
MAX 9000A
MAX 9000
Programmable Logic
Device Family
Data Sheet
November 2001, ver. 6.3
Features...
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High-performance CMOS EEPROM-based programmable logic
devices (PLDs) built on third-generation Multiple Array MatriX
(MAX
®
) architecture
5.0-V in-system programmability (ISP) through built-in IEEE Std.
1149.1 Joint Test Action Group (JTAG) interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE
Std. 1149.1-1990
High-density erasable programmable logic device (EPLD) family
ranging from 6,000 to 12,000 usable gates (see
Table 1)
10-ns pin-to-pin logic delays with counter frequencies of up to
144 MHz
Fully compliant with the peripheral component interconnect Special
Interest Group’s (PCI SIG)
PCI Local Bus Specification, Revision 2.2
Dual-output macrocell for independent use of combinatorial and
registered logic
FastTrack
®
Interconnect for fast, predictable interconnect delays
Input/output registers with clear and clock enable on all I/O pins
Programmable output slew-rate control to reduce switching noise
MultiVolt
™
I/O interface operation, allowing devices to interface
with 3.3-V and 5.0-V devices
Configurable expander product-term distribution allowing up to 32
product terms per macrocell
Programmable power-saving mode for more than 50% power
reduction in each macrocell
Table 1. MAX 9000 Device Features
Feature
Usable gates
Flipflops
Macrocells
Logic array blocks (LABs)
Maximum user I/O pins
t
PD1
(ns)
t
FSU
(ns)
t
FCO
(ns)
f
CNT
(MHz)
EPM9320
EPM9320A
6,000
484
320
20
168
10
3.0
4.5
144
EPM9400
8,000
580
400
25
159
15
5
7
118
EPM9480
10,000
676
480
30
175
10
3.0
4.8
144
EPM9560
EPM9560A
12,000
772
560
35
216
10
3.0
4.8
144
Altera Corporation
A-DS-M9000-6.3
1
MAX 9000 Programmable Logic Device Family Data Sheet
...and More
Features
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Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
Programmable security bit for protection of proprietary designs
Software design support and automatic place-and-route provided by
Altera’s MAX+PLUS
®
II development system on Windows-based
PCs as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM
RISC System/6000 workstations
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,
OrCAD, Synopsys, Synplicity, and VeriBest
Programming support with Altera’s Master Programming Unit
(MPU), BitBlaster
TM
serial download cable, ByteBlaster
TM
parallel
port download cable, and ByteBlasterMV
TM
parallel port download
cable, as well as programming hardware from third-party
manufacturers
Offered in a variety of package options with 84 to 356 pins (see
Table 2)
Note (1)
304-Pin
RQFP
–
–
–
–
216
–
Table 2. MAX 9000 Package Options & I/O Counts
Device
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
Notes:
(1)
84-Pin
PLCC
60
(2)
60
(2)
59
(2)
–
–
–
208-Pin
RQFP
132
132
139
146
153
153
240-Pin
RQFP
–
–
159
175
191
191
280-Pin
PGA
168
–
–
–
216
–
356-Pin
BGA
168
168
–
–
216
216
(2)
MAX 9000 device package types include plastic J-lead chip carrier (PLCC), power
quad flat pack (RQFP), ceramic pin-grid array (PGA), and ball-grid array (BGA)
packages.
Perform a complete thermal analysis before committing a design to this device
package. See
Application Note 74 (Evaluating Power for Altera Devices).
2
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
General
Description
The MAX 9000 family of in-system-programmable, high-density, high-
performance EPLDs is based on Altera’s third-generation MAX
architecture. Fabricated on an advanced CMOS technology, the EEPROM-
based MAX 9000 family provides 6,000 to 12,000 usable gates, pin-to-pin
delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed
grade of the MAX 9000 family is compliant with the
PCI Local Bus
Specification, Revision 2.2.
Table 3
shows the speed grades available for
MAX 9000 devices.
Table 3. MAX 9000 Speed Grade Availability
Device
-10
EPM9320
EPM9320A
EPM9400
EPM9480
EPM9560
EPM9560A
Speed Grade
-15
v
v
v
v
v
v
v
v
v
-20
v
Table 4
shows the performance of MAX 9000 devices for typical functions.
Table 4. MAX 9000 Performance
Application
Note (1)
Macrocells Used
-10
16-bit loadable counter
16-bit up/down counter
16-bit prescaled counter
16-bit address decode
16-to-1 multiplexer
Note:
(1)
Internal logic array block (LAB) performance is shown. Numbers in parentheses show external delays from row
input pin to row I/O pin.
Speed Grade
-15
118
118
118
7.9 (15)
10.9 (18)
Units
-20
100
100
100
10 (20)
16 (26)
MHz
MHz
MHz
ns
ns
16
16
16
1
1
144
144
144
5.6 (10)
7.7 (12.1)
The MAX 9000 architecture supports high-density integration of system-
level logic functions. It easily integrates multiple programmable logic
devices ranging from PALs, GALs, and 22V10s to field-programmable
gate array (FPGA) devices and EPLDs.
Altera Corporation
3
MAX 9000 Programmable Logic Device Family Data Sheet
All MAX 9000 device packages provide four dedicated inputs for global
control signals with large fan-outs. Each I/O pin has an associated I/O
cell register with a clock enable control on the periphery of the device. As
outputs, these registers provide fast clock-to-output times; as inputs, they
offer quick setup times.
MAX 9000 EPLDs provide 5.0-V in-system programmability (ISP). This
feature allows the devices to be programmed and reprogrammed on the
printed circuit board (PCB) for quick and efficient iterations during design
development and debug cycles. MAX 9000 devices are guaranteed for 100
program and erase cycles.
MAX 9000 EPLDs contain 320 to 560 macrocells that are combined into
groups of 16 macrocells, called logic array blocks (LABs). Each macrocell
has a programmable-AND/fixed-OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. For increased flexibility, each macrocell offers a dual-output
structure that allows the register and the product terms to be used
independently. This feature allows register-rich and combinatorial-
intensive designs to be implemented efficiently. The dual-output
structure of the MAX 9000 macrocell also improves logic utilization, thus
increasing the effective capacity of the devices. To build complex logic
functions, each macrocell can be supplemented with both shareable
expander product terms and high-speed parallel expander product terms
to provide up to 32 product terms per macrocell.
The MAX 9000 family provides programmable speed/power
optimization. Speed-critical portions of a design can run at high
speed/full power, while the remaining portions run at reduced
speed/low power. This speed/power optimization feature enables the
user to configure one or more macrocells to operate at 50% or less power
while adding only a nominal timing delay. MAX 9000 devices also
provide an option that reduces the slew rate of the output buffers,
minimizing noise transients when non-speed-critical signals are
switching. MAX 9000 devices offer the MultiVolt feature, which allows
output drivers to be set for either 3.3-V or 5.0-V operation in mixed-
voltage systems.
4
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
The MAX 9000 family is supported by Altera’s MAX+PLUS II
development system, a single, integrated software package that offers
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The MAX+PLUS II software provides EDIF 2 0 0
and 3 0 0, LPM, and other interfaces for additional design entry and
simulation support from other industry-standard PC- and UNIX-
workstation-based EDA tools. The MAX+PLUS II software runs on
Windows-based PCs as well as Sun SPARCstation, HP 9000 Series
700/800, and IBM RISC System/6000 workstations.
f
Functional
Description
For more information on development tools, see the
MAX+PLUS II
Programmable Logic Development System & Software Data Sheet.
MAX 9000 devices use a third-generation MAX architecture that yields
both high performance and a high degree of utilization for most
applications. The MAX 9000 architecture includes the following elements:
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Logic array blocks
Macrocells
Expander product terms (shareable and parallel)
FastTrack Interconnect
Dedicated inputs
I/O cells
Figure 1
shows a block diagram of the MAX 9000 architecture.
Altera Corporation
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