PD-97530C
(5962F1023503K)
IRUH330118AK
Radiation Hardended Ultra Low Dropout
IRUH330118AP
Fixed Positive Linear Regulator
+3.3V
IN
to +1.8V
OUT
@3.0A
Product Summary
Part Number
IRUH330118AK
IRUH330118AP
I
O
3.0A
V
IN
3.3V
V
OUT
1.8V
8-LEAD FLAT PACK
Description
The IRUH330118 is a space qualified, ultra low dropout
linear regulator designed specifically for applications
requiring high reliability, low noise and radiation hardness.
Features
n
Silicon On Insulator (SOI) CMOS Regulator
n
n
n
n
n
n
n
n
n
n
Absolute Maximum Ratings
Parameter
Power Dissipation @ T
C
= 125°C
Maximum Output Current @ Maximum
Power Dissipation with no Derating
Non-Operating Input Voltage
Operating Input Voltage
Ground
Shutdown Pin Voltage
Output Pin Voltage
Operating Case Temperature Range
Storage Temperature Range
Maximmum Junction Temperature
Lead Temperature (Soldering 10sec)
Pass Transistor Thermal Resistance, Junction to Case
P
D
I
O
V
IN
V
IN
GND
V
SHDN
V
OUT
T
O
T
S
T
J
R
THJC
T
L
IC, CMOS Latch-Up Immune,
Inherently Rad Hard
Total Dose Capability up to 300Krads(Si)
(Condition A); Tested to 500Krad (Si)
ELDRS up to 100Krad(Si) (Condition D)
SEU Immune up to LET = 80 MeV*cm
2
/mg
Space Level Screened
Fast Transient Response
Timed Latch-Off Over-Current Protection
Internal Thermal Protection
On/Off Control via Shutdown Pin, Power
Sequencing Easily Implemented
Isolated Hermetic 8-Lead Flat Pack
Ensures Higher Reliability
This part is also available in MO-078 Package
as IRUH330118BK / IRUH330118BP
Min.
-
-
-0.3
2.9
-0.3
-0.3
-0.3
-55
-65
-
-
-
Symbol
Max.
25
See Fig 4
+8.0
6.4
0.3
V
IN
+ 0.3
V
IN
+ 0.3
+140
+150
+150
+300
1.0
Units
W
A
V
°C
°C/W
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1
05/18/12
IRUH330118AK
IRUH330118AP
Electrical Characteristics
c
Pre-Radiation @T
C
= 25°C, V
IN
= 3.3V
(Unless Otherwise Specified)
Parameter
Test Conditions
2.8V
≤
V
IN
≤
3.8V, 50mA
≤
I
OUT
≤
3.0A
2.8V
≤
V
IN
≤
3.8V, 50mA
≤
I
OUT
≤
3.0A,
-55°C to +125°C
2.8V
≤
V
IN
≤
3.8V, 50mA
≤
I
OUT
≤
3.0A,
Post -Rad
Current Limit
Over-Current Time-to-Latch
Maximum Shutdown Temp.
Ripple Rejection
Over-Current Latching, -55°C to +125°C,
Post -Rad
I
O
> I
LATCH
F= 120Hz, I
O
= 50mA, -55°C to +125°C
F= 120Hz, I
O
= 50mA, Post -Rad
-55°C to +125°C
I
SOURCE
= 200µA, -55°C to +125°C
Post -Rad
I
SOURCE
= 200µA, -55°C to +125°C
Post -Rad
R
LOAD
= 36 Ohms, V
SHDN
= 3.3V
I
LATCH
t
LATCH
T
LATCH
PSRR
I
SENSE
V
SHDN
V
SHDN
V
OUT
I
SHDN
I
SHDN
V
T-POR
I
Q
V
OUT
Symbol
Min.
1.773
1.746
1.737
3.5
-
125
65
40
-
-
1.2
-0.1
-10
-98
-140
-98
-
-
-
Typ. Max. Units
1.8
1.8
1.8
-
10
140
-
-
1.6
-
-
-
-
-
-
-
1.7
-
-
1.827
1.854
1.836
-
-
-
-
-
-
0.8
-
0.1
10
-56
-30
-56
-
15
90
V
mA
A
ms
°C
dB
mA
V
V
V
µA
µA
V
Output Voltage
c
d
d
V
SENSE
Pin Current
Threshold Voltage
d
Minimum SHDN Pin "On"
Maximum SHDN Pin "Off"
Threshold Voltage
Output Voltage at Shutdown
SHDN Pin Leakage Current
SHDN Pin Pull-Up Current
d
-55°C to +125°C, Post-Rad
V
SHDN
= 3.3V, -55°C to +125°C,Post-Rad
V
SHDN
= 0.4V
V
SHDN
= 0.4V, -55°C to +125°C
V
SHDN
= 0.4V, Post-Rad
Sweep V
IN
and Measure Output
No Load
Full Load
d
Power On Reset Threshold
d
Quiescent Current
d
Notes:
Connected as shown in Fig.1 and measured at the junction of V
OUT
and V
SENSE
Pins.
Under normal closed-loop operation. Guaranteed by design. Not tested in production.
2
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IRUH330118AK
IRUH330118AP
Radiation Performance Characteristics
Test
Total Ionizing Dose (Gamma)
Conditions
MIL-STD-883, Method 1019 (Condition A)
Operating Bias applied during exposure
Minimum Rated Load, Vin = 6.4V
MIL-STD-883, Method 1019 (Condition D)
Min
300
Typ
500
Unit
Krads (Si)
c
d
Total Ionizing Dose (Gamma)
Single Event effects
SEU, SEL, SEGR, SEB
(ELDRS) Operating Bias applied during
exposure Minimum Rated Load, Vin = 6.4V
Heavy Ions (LET)
Operating Bias applied during exposure
under varying operating conditions
100
See
Krads (Si)
84
MeV*cm /mg
2
Neutron Fluence
MIL-STD-883, Method 1017
1.0e
11
Neutrons/cm
2
Notes:
Tested to 500Krad (Si).
See Fig. 5.
Space Level Screening Requirements
TEST/INSPECTION
SCREENING LEVEL
SPACE
Nondestructive Bond Pull
Internal Visual
Seal
Temperature Cycle
Constant Acceleration
Mechanical Shock
PIND
Pre Burn-In-Electrical
Burn-In
Final Electrical
Radiographic
External Visual
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
2012
2009
1015
MIL-STD-883
METHOD
2023
2017
1014
1010
2001
2002
2020
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3
IRUH330118AK
IRUH330118AP
Application Information
Input
Voltage
0.1uF and 1uF
Ceramic;
Two 100uF
Low ESR
Tantalum
V
IN
V
OUT
Output
Voltage
0.1uF and 1uF
Ceramic;
Two 100uF
Low ESR
Tantalum
IRUH3301xxxx
SHDN
GND
V
SENSE
Fig. 1.
Typical Regulator Circuit; Note the SHDN Pin is hardwired in the “ON” position.
The V
SENSE
Pin is connected as noted in the “General Layout Rules” section.
Over-Current & Over-Temperature Protection
The IRUH3301 series provides over-current protection by means of a timed latch function. Drive
current to the internal PNP pass transistor is limited by an internal resistor (Rb in Fig. 3) between
the base of the transistor and the control IC drive FET.
If an over-current condition forces the
voltage across this resistor to exceed 0.5V (nom), the latch feature will be triggered. The time-to-
latch (t
LATCH
) is nominally 10ms. If the over-current condition exists for less than t
LATCH
, the latch
will not be set. If the latch is set the drive current to the PNP pass transistor will be disabled. The
latch will remain set until one of the following actions occur:
1. The SHDN Pin voltage is brought above 1.2V and then lowered below 0.8V.
2. The V
IN
Pin voltage is lowered below 1.7V.
If the junction temperature of the regulator IC exceeds 140°C nominal, the thermal shutdown circuit
will set the internal latch and disable the drive current to the PNP pass transistor as described
above. After the junction temperature falls below a nominal 125°C, the latch can be reset using
either of the actions described above.
Under-Voltage Lock-Out
The under-voltage lock-out (UVLO) function prevents operation when
V
IN
is less than 1.7V
(nominal). There is a nominal 100mV hysteresis about this point.
Input Voltage Range
The device functions fully when
V
IN
is greater than 2.8V. It enters into under-voltage lock-out at
V
IN
< 1.7V (nominal). When 1.7V (nominal) <
V
IN
< 2.8V,
V
OUT
will track
V
IN
and overshoot may occur.
A larger output capacitor should be used to slow down the
V
OUT
rise rate for slow
V
IN
ramp
applications.
Shutdown (SHDN)
The regulator can be shutdown by applying a voltage of >1.2V to the SHDN Pin. The regulator will
restart when the SHDN Pin is pulled below the shutdown threshold of 0.8V. If the remote shutdown
feature is not required, the SHDN Pin should be connected to GND.
4
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IRUH330118AK
IRUH330118AP
Input Capacitance
Input bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX
TPS or equivalent), placed very close to the V
IN
Pin are required for proper operation. When the
input voltage supply capacitance is more than 4 inches from the device, additional input
capacitance is recommended. Larger input capacitor values will improve ripple rejection further
improving the integrity of the output voltage.
Output Capacitance
Output bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums
(AVX TPS or equivalent)
are required for loop stability. Faster transient performance can be
achieved with multiple additional 1µF ceramic capacitors. Ceramic capacitors greater than 1µF in
value are not recommended as they can cause stability issues.
Tantalum capacitor values larger than the suggested value are recommended to improve the
transient response under large load current changes. The upper capacitance value limit is
governed by the delayed over-current latch function of the regulator and
can be as much as
10,000µF without causing the device to latch-off during start-up.
General Layout Rules
Low impedance connections between the regulator output and load are essential. Solid power and
ground planes are highly recommended. In those cases where the board impedances are not kept
very small, oscillations can occur due to the effect of parasitic series resistance and inductance
on loop bandwidth and phase margin.
The V
SENSE
Pin must be connected directly to the
V
OUT
Pin using as short a trace as possible with
the connection inside the first bypass capacitor (see Fig. 2a).
Connect ceramic output capacitors directly across the V
OUT
and GND Pins with as wide a trace as
design rules allow (see Fig. 2a). Avoid the use of vias for these capacitors and avoid loops. Fig.2
shows the ceramic capacitors tied directly to the regulator output.
The input capacitors should be connected as close a possible to the V
IN
Pin.
Fig. 2a.
Layer 1 conductor.
Ground plane below layer 1
Fig. 2b.
Layer 1 silkscreen
5
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