Data Sheet No. PD60277
IRS2304(S)PbF
Features
•
•
•
•
•
•
•
•
•
•
Floating channel designed for bootstrap operation
to +600 V
Tolerant to negative transient voltage, dV/dt
immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout for both channels
3.3 V, 5 V, and 15 V input logic input compatible
Cross-conduction prevention logic
Matched propagation delay for both channels
Lower di/dt gate driver for better noise immunity
Internal 100 ns deadtime
Output in phase with input
HALF-BRIDGE DRIVER
Product Summary
V
OFFSET
I
O+/-
(min)
V
OUT
Delay Matching
Internal deadtime
t
on/off
(typ.)
600 V max.
60 mA/130 mA
10 V - 20 V
50 ns
100 ns
150 ns/150 ns
(ns)2106/2301COM21064HIN/LINnononeVSS/COM220/200
2108Internal 540COM21084HIN/LINyes
Ground Pins
ton/toff
Progra
IGBT in thehigh-side configuration which oper-
LIN
HIN
VCC
COM
VB
HO
VS
LO
The floating chan-nel can be used to drive an N-chan-
pulse current bufferstage designed for minimum driver
MOS or LSTTL output,down to 3.3 V logic. The output driver
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zed monolithic construction.The logic input is compatible with
low-side referenced output channels. ProprietaryHVIC and latch immune CMOS technologies enable
IRS2304(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
V
S
V
B
V
HO
V
CC
V
LO
V
IN
Com
dV
S
/dt
P
D
Rth
JA
T
J
T
S
T
L
High- side offset voltage
Definition
High- side floating supply voltage
High- side floating output voltage HO
Low- side and logic fixed supply voltage
Low- side output voltage LO
Logic input voltage (HIN, LIN)
Logic ground
Allowable offset supply voltage transient
Package power dissipation @ T
A
≤
+25 °C
Thermal resistance, junction to ambient
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
8-Lead SOIC
8-Lead PDIP
8-Lead SOIC
8-Lead PDIP
Min.
V
B
- 25
-0.3
V
S
- 0.3
-0.3
-0.3
-0.3
V
CC
-25
—
—
—
—
—
—
-50
—
Max.
V
B
+ 0.3
625
V
B
+ 0.3
25
V
CC
+ 0.3
V
CC
+ 0.3
V
CC
+ 0.3
50
0.625
1.0
200
125
150
150
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The V
S
offset rating is tested with all supplies biased at 15 V differential.
Symbol
V
B
V
S
V
HO
V
LO
V
IN
V
CC
T
A
Definition
High- side floating supply voltage
High- side floating supply offset voltage
High-side (HO) output voltage
Low- side (LO) output voltage
Logic input voltage (HIN, LIN)
Low- side supply voltage
Ambient temperature
Min.
V
S
+ 10
Note 1
V
S
COM
COM
10
-40
Max.
V
S
+ 20
600
V
B
V
CC
V
CC
20
125
Units
V
°C
Note 1:
Logic operational for V
S
of COM -5 V to COM +600 V. Logic state held for V
S
of COM -5 V to COM -V
BS
.
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IRS2304(S)PbF
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V and T
A
= 25 °C unless otherwise specified. The V
IN
, V
TH,
and I
IN
parameters are referenced to
COM. The V
O
and I
O
parameters are referenced to COM and V
S
is applicable to HO and LO.
Symbol
V
CCUV+
V
BSUV+
V
CCUV-
V
BSUV-
V
CCUVH
V
BSUVH
I
LK
I
QBS
I
QCC
V
IH
V
IL
V
OH
V
OL
I
IN+
I
IN-
I
O+
I
O-
Definition
V
CC
and V
BS
supply undervoltage positive going
threshold
V
CC
and V
BS
supply undervoltage negative going
threshold
V
CC
supply undervoltage lockout hysteresis
Offset supply leakage current
Quiescent V
BS
supply current
Quiescent V
CC
supply current
Logic “1” input voltage
Logic “0” input voltage
High level output voltage, V
BIAS
- V
O
Low level output voltage, V
O
Logic “1” input bias current
Logic “0” input bias current
Output high short circuit pulse current
Output low short circuit pulsed current
Min. Typ. Max. Units Test Conditions
8
7.4
0.3
—
20
50
2.3
—
—
—
—
—
60
130
8.9
8.2
0.7
—
60
120
—
—
0.05
0.02
5
1.0
290
600
9.8
9
—
50
150
240
—
0.7
0.2
0.1
40
5.0
—
—
mA
µA
V
I
O
= 2 mA
V
IN
= 5 V
V
IN
= 0 V
V
O
= 0 V
PW
≤
10 µs
µA
V
B
= V
S
= 600 V
V
IN
= 0 V or 5 V
V
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS
) = 15 V, V
S
= COM, C
L
= 1000 pF and T
A
= 25 °C unless otherwise specified.
Symbol
ton
toff
tr
tf
DT
MT
Definition
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
Turn-off fall time
Deadtime
Delay matching, HS & LS turn-on/off
Min. Typ. Max. Units Test Conditions
90
90
—
—
80
—
150
150
70
35
100
—
210
210
120
60
190
50
ns
V
S
= 0 V
V
S
= 0 V or 600 V
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IRS2304(S)PbF
Functional Block Diagram
VB
2304
HIN
PULSE
GENERATOR
HV
LEVEL
SHIFTER
UV
DETECT
R
PULSE
FILTER
R
S
Q
HO
VS
SHOOT-
THROUGH
PREVENTION
VCC
UV
DETECT
LO
LIN
DELAY
COM
Lead Definitions
Symbol
V
CC
COM
HIN
LIN
V
B
HO
V
S
LO
Description
Low-side supply voltage
Logic ground and low-side driver return
Logic input for high-side gate driver output
Logic input for low-side gate driver output
High-side floating supply
High-side driver output
High voltage floating supply return
Low-side driver output
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IRS2304(S)PbF
Lead Assignments
1
LIN
VB
8
1
LIN
VB
8
2
HIN
HO
7
2
HIN
HO
7
3
VCC
VS
6
3
VCC
VS
6
4
COM
LO
5
4
COM
LO
5
8-Lead PDIP
8-Lead SOIC
HIN
LIN
HO
Internal Deadtime
LO
Figure 1. Input/Output Functionality Diagram
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