DATASHEET
VCXO AND MULTIPLIER
Description
The MK3732-10 is a low cost, low jitter, high performance
VCXO and PLL clock synthesizer designed to replace
expensive discrete VCXOs and multipliers. The patented
on-chip Voltage Controlled Crystal Oscillator accepts a 0 to
3.3 V input voltage to cause the output clocks to vary by
±115 ppm. Using IDT’ analog/digital Phase-Locked Loop
(PLL) techniques, the device uses an inexpensive 27 MHz
pullable crystal input to produce three output clocks.
IDT manufactures the largest variety of MPEG clock
synthesizers for all applications. Consult IDT to eliminate
VCXOs, crystals, and oscillators from your board.
MK3732-10
Features
•
•
•
•
•
•
Packaged in 16 pin SOIC
Replaces a VCXO and oscillator
Contains popular multiplier values
Uses an inexpensive 27 MHz pullable crystal
Includes popular audio frequencies from 27 MHz
On-chip patented VCXO with pull range of 230 ppm
(±115 ppm) minimum
•
VCXO tuning voltage of 0 to 3.3 V
•
Advanced, low power, sub-micron CMOS process
•
Operating voltage of 3.3 V
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
VDD
2
PDCLK3
S3:S0
VIN
X1
16 - 28 MHz
Pullable
Crystal
4
PLL/Clock
Synthesis
Circuitry
CLK
REF/2
Voltage
Controlled
Crystal
Oscillator
2
/2
REF
X2
GND
OE (all outputs)
IDT™
VCXO AND MULTIPLIER
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VCXO AND MULTIPLIER
Pin Assignment
X1
VDD
VDD
VIN
GND
GND
S3
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
OE
S1
REF/2
REF
CLK3
S0
PDCLK3
16 Pin (150 mil) SOIC
Clock Select Table
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16 - 28
16 - 28
16 - 28
16 - 27
27
27
27
27
REF/2
REF/2
REF/2
REF/2
13.5
13.5
13.5
13.5
Input
16 - 28
16 - 28
16 - 28
16 - 28
16 - 28
16 - 28
16 - 28
CLK1
REF/2
REF/2
REF/2
REF/2
REF/2
REF/2
REF/2
CLK2
REF
REF
REF
REF
REF
REF
REF
TEST
REF
REF
REF
REF
27
27
27
27
64 - 112
80 - 140
85 - 150
96 - 162
11.289
12.288
8.192
24.576
x4
x5
x5.333
x6
N/A
N/A
N/A
N/A
CLK3
20 - 35
21 - 37.5
24 - 42
32 - 56
40 - 70
42 - 75
48 - 84
Multiplier
x1.25
x1.333
x1.5
x2
x2.5
x2.667
x3
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Pin Descriptions
Pin
Number
1
2-3
4
5-6
7
8
9
10
11
12
13
14
15
16
Pin
Name
XI
VDD
VIN
GND
S3
S2
PDCLK3
S0
CLK3
REF
REF/2
S1
OE
X2
Pin
Type
XI
Power
Input
Power
Input
Input
Input
Input
Output
Output
Output
Input
Input
XO
Connect to +3.3 V.
Pin Description
Crystal connection. Connect to a pullable of 16 to 28 MHz cyrstal.
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency.
Connect to ground.
Select input #3. Selects outputs per table above. Internal pull-up resistor.
Select input #2. Selects outputs per table above. Internal pull-up resistor.
Power down for CLK3.
Select input #0. Selects outputs per table above. Internal pull-up resistor.
PLL output clock that is either a multiple of the input or an audio clock. See table
above.
Buffered VCXO reference clock output. Matches crystal frequency.
Reference clock output divided by two.
Select input #1. Selects outputs per table above. Internal pull-up resistor.
Output enable. Tri-states outputs when low. Internal pull-up resistor.
Crystal connection. Connect to a pullable 16 to 28 MHz crystal.
Pin Descriptions
The MK3732-10 requires a minimum number of external
components for proper operation.
crystal and the integrated VCXO oscillator circuit. To assure
the best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section must be
followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
MK3732-10 incorporates on-chip variable load capacitors
that “pull” (change) the frequency of the crystal. The crystal
specified for use with the MK3732-10 is designed to have
zero frequency error when the total of on-chip + stray
capacitance is 14pF.
Decoupling Capacitors
Decoupling capacitors of 0.01µF should be connected
between VDD and GND on pins 2 and 5 and pins 3 and 6,
as close to the MK3732-10 as possible. For optimum device
performance, the decoupling capacitors should be mounted
on the component side of the PCB. Avoid the use of vias in
the decoupling circuit.
Series Termination Resistor
When the PCB traces between the clock outputs (CLK, pin
5) and the loads are over 1 inch, series termination should
be used. To series terminate a 50Ω trace (a commonly used
trace impedance) place a 33Ω resistor in series with the
clock line, as close to the clock output pin as possible. The
nominal impedance of the clock output is 20Ω
.
Quartz Crystal
The MK3732-10 VCXO function consists of the external
Recommended Crystal Parameters:
Initial Accuracy at 25
°
C
Temperature Stability
±20 ppm
±30 ppm
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Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
±20 ppm
14 pf
7 pF Max
250 Max
35
Ω
Max
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
The procedure for determining the value of these capacitors
can be found in application note MAN05.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the MK3732-10. There should be no via’s between the
crystal pins and the X1 and X2 device pins. There should be
no signal traces underneath or close to the crystal.
See
application note MAN05.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3732-10. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Soldering Temperature
7V
Rating
-0.5V to VDD+0.5V
0 to +70° C
-65 to +150° C
260° C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Reference crystal parameters
Min.
0
+3.15
Typ.
3.3
Max.
+70
+3.45
Units
°
C
V
Refer to pages 3 - 4
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DC Electrical Characteristics
VDD=3.3V ±5%
, Ambient temperature 0 to +70° C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Short Circuit Current
Input Capacitance
Frequency Synthesis Error
VIN, VCXO Control Voltage
V
IA
C
IN
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
Conditions
X1 pin, clock in
Non VCXO mode
X1 pin, clock in
Non VCXO mode
Min.
3.15
(VDD/2)+1
Typ.
3.3
Max.
3.45
Units
V
V
(VDD/2)-1
2
0.8
V
V
V
V
V
V
I
OH
= -12 mA
I
OL
= 12 mA
I
OH
= -4 mA
No Load
Each output
S2:S0, OE
All clocks
2.4
0.4
-0.5
19
±50
5
0
0
3.3
mA
mA
pF
ppm
V
AC Electrical Characteristics
VDD = 3.3V ±5%
, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Input Crystal Frequency
Output Clock Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Maximum Absolute Jitter
Output pullability
0V < VIN < 3.3V, Note 1
±115
Symbol
f
IN
f
OUT
Conditions
Min.
16
8
Typ.
27
1.5
1.5
Max. Units
28
162
MHz
MHz
ns
ns
60
%
ps
ppm
0.8 to 2.0V
2.0 to 0.8V
at VDD/2
40
±350
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on pages 3-4.
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