TSPC603R
PowerPC 603e RISC Microprocessor
Family PID7t-603e
Datasheet
Features
•
•
•
•
•
•
•
Superscalar (3 Instructions per Clock Peak)
Dual 16 KB Caches
Selectable Bus Clock
32-bit Compatibility PowerPC Implementation
On-chip Debug Support
Nap, Doze and Sleep Power Saving Modes
Device Offered in Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255
Features Specific to CBGA 255, HiTCE CBGA 255 and CI-CGA 255
•
•
•
•
•
•
•
•
•
•
•
7.4 SPECint95, 6.1 SPECfp95 at 300 MHz (Estimated)
P
D
Typically = 3.5W (266 MHz), Full Operating Conditions
Branch Folding
64-bit Data Bus (32-bit Data Bus Option)
4-Gbytes Direct Addressing Range
Pipelined Single/Double Precision Float Unit
IEEE 754 Compatible FPU
IEEE P 1149-1 Test Mode (JTAG/C0P)
f
INT
Max = 300 MHz
f
BUS
Max = 75 MHz
Compatible CMOS Input/TTL Output
Features Specific to Cerquad
•
5.6 SPECint95, 4 SPECfp95 and 200 MHz (Estimated)
•
P
D
Typically = 2.5W (200 MHz), Full Operating Conditions
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for the latest version of the datasheet
e2v semiconductors SAS 2011
0841D–HIREL–05/11
TSPC603R
1. Description
The PID7t-603e implementation of the PowerPC 603e (renamed after the 603R) is a low-power imple-
mentation of the Reduced Instruction Set Computer (RISC) microprocessor PowerPC family. The 603R
is pin-to-pin compatible with the PowerPC 603e and 603P in a Cerquad package. The 603R implements
32-bit effective addresses, integer data types of 8, 16 and 32 bits, and floating-point data types of 32 and
64 bits.
The 603R is a low-power 2.5/3.3V design and provides four software controllable power-saving modes.
This device is a superscalar processor capable of issuing and retiring as many as three instructions per
clock. Instructions can be executed in any order for increased performance, but, the 603R makes com-
pletion appear sequential. It integrates five execution units and is able to execute five instructions in
parallel.
The 603R provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed
caches for instructions and data, as well as on-chip instructions, and data Memory Management Units
(MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation look
aside buffers that provide support for demand-paged virtual memory address translation and vari-
able-sized block translation. The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus.
The interface protocol allows multiple masters to compete for system resources through a central exter-
nal arbiter. The device supports single-beat and burst data transfers for memory accesses, and supports
memory-mapped I/Os.
The 603R uses an advanced, 2.5/3.3V CMOS process technology and maintains full interface compati-
bility with TTL devices. It also integrates in-system testability and debugging features through JTAG
boundary-scan capabilities.
2. Screening/Quality/Packaging
This product is manufactured in full compliance with:
• HiTCE CBGA according to e2v Standards
• CI-CGA 255 and Cerquad: MIL-PRF-38535 class Q or according to e2v standards
• CBGA 255: Upscreenings based upon e2v standards
• CBGA, CI-CGA, HiTCE packages:
– Full military temperature range (T
C
= -55°C, T
j
= +125°C)
– Industrial temperature range
• Cerquad:
– Full military temperature range (T
C
= -55°C, T
c
= +125°C)
– Industrial temperature range
(T
C
= -40°C, T
c
= +110°C)
– Commercial temperature ranges (
T
C
= 0° C,
T
C
= +70° C)
• Internal I/O Power Supply = 2.5 ±5% // 3.3V ±5%
(T
C
= -40°C, T
j
= +110°C)
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TSPC603R
3. Block Diagram
Figure 3-1.
Block Diagram
Fetch
Unit
Completion
Unit
Dispatch
Unit
Branch
Unit
Integer
Unit
Gen
Reg
Unit
Gen
Re-
name
Load/
Store
Unit
FP
Re-
name
FP
Reg
File
Float
Unit
D MMU
16K Data Cache
I MMU
16K Inst. Cache
Bus Interface Unit
32b Address
System Bus
64b Data
4. Overview
The 603R is a low-power implementation of the PowerPC microprocessor family of Reduced Instruction
Set Computing (RISC) microprocessors. The 603R implements the 32-bit portion of the PowerPC archi-
tecture, which provides 32-bit effective addresses, integer data types of 8, 16 and 32 bits, and
floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architec-
ture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the
64-bit architecture.
The 603R provides four software controllable power-saving modes. Three of the modes (nap, doze, and
sleep) are static in nature, and progressively reduce the amount of power dissipated by the processor.
The fourth is a dynamic power management mode that causes the functional units in the 603R to auto-
matically enter a low-power mode when the functional units are idle without affecting operational
performance, software execution, or any external hardware.
The 603R is a superscalar processor capable of issuing and retiring as many as three instructions per
clock. Instructions can be executed in any order for increased performance, but, the 603R makes com-
pletion appear sequential.
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0841D–HIREL–05/11
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TSPC603R
The 603e integrates five execution units:
• an Integer Unit (IU)
• a Floating-point Unit (FPU)
• a Branch Processing Unit (BPU)
• a Load/Store Unit (LSU)
• a System Register Unit (SRU)
The ability to execute five instructions in parallel and the use of simple instructions with rapid execution
times yield high efficiency and throughput for 603R-based systems. Most integer instructions execute in
one clock cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every
clock cycle.
The 603R provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed
caches for instructions and data, as well as on-chip instruction and data Memory Management Units
(MMUs). The MMUs contain 64-entry, two-way set-associative, Data and Instruction Translation Looka-
side Buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation
and variable-sized block translation. The TLBs and caches use a Least Recently Used (LRU) replace-
ment algorithm. The 603R also supports block address translation through the use of two independent
Instruction and Data Block Address Translation (IBAT and DBAT) arrays of four entries each. Effective
addresses are compared simultaneously with all four entries in the BAT array during block translation. In
accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array,
the BAT translation has priority.
The 603R has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603R interface protocol
allows multiple masters to compete for system resources through a central external arbiter. The 603R
provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache
states. This protocol is a compatible subset of the MESI (Modified/Exclusive/Shared/Invalid) four-state
protocol and operates coherently in systems that contain four-state caches. The 603R supports sin-
gle-beat and burst data transfers for memory accesses, and supports memory-mapped I/Os.
The 603R uses an advanced, 0.29 µm 5-metal-layer CMOS process technology and maintains full inter-
face compatibility with TTL devices.
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TSPC603R
5. Signal Description
Figure 5-1, Table 10-5
and
Table 10-6 on page 21
describe the signals on the TSPC603R and indicate
signal functions. The test signals, TRST, TMS, TCK, TDI and TDO, comply with the subset P-1149.1 of
the IEEE testability bus standard.
The three signals LSSD_MODE, LI_TSTCLK and L2_TSTCLK are test signals for factory use only and
must be pulled up to V
DD
for normal machine operations.
Figure 5-1.
Functional Signal Groups
BR
ADDRESS
ARBITRATION
BG
ABB
1
1
1
1
1
1
DBG
DBWO
DBB
DATA
ATTRIBUTION
ADDRESS
START
TS
1
64
8
DH[0-31], DL[0-31]
DP[0-7]
DPE
DBDIS
TA
DR TR Y
TEA
INT, SMI
MCP
CKSTP_IN, CKSTP_OUT
HRESET, SRESET
RSRV
QREQ, QACK
TBEN
TLBISYNC
PROCESSOR
STATUS
INTERRUPTS
CHECKSTOPS
RESET
DATA
TERMINATION
DATA
TRANSFER
A[0-31]
ADDRESS
BUS
AP[0-3]
APE
TT[0-4]
TBST
TSIZ[0-2]
GBL
TRANSFER
ATTRIBUTE
CI
WT
CSE[0-1]
TC[0-1]
32
4
1
5
1
3
1
1
1
2
2
603r
1
1
1
1
1
2
1
2
2
1
2
1
ADDRESS
TERMINATION
AACK
ARTRY
1
1
1
5
TRST, TCK, TMS, TDI, TD0
LSSD_MODE
L1_TSTCLK, L2_TSTCLK
VDD
OVDD
GND
AVDD
JTAG/COP
INTERFACE
LSSD TEST
CONTROL
SYSCLK
CLOCKS
CLK_OUT
PLL_CFG[0-3]
POWER SUPPLY
INDICATOR
VOLTDETGND
1
1
4
20
1
19
40
1
3
POWER SUPPLY
5
0841D–HIREL–05/11
e2v semiconductors SAS 2011
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