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SNJ54AS866FK

产品描述Magnitude Comparator, AS Series, 8-Bit, True Output, TTL, CQCC28, QFN-28
产品类别逻辑    逻辑   
文件大小116KB,共7页
制造商Rochester Electronics
官网地址https://www.rocelec.com/
下载文档 详细参数 选型对比 全文预览

SNJ54AS866FK概述

Magnitude Comparator, AS Series, 8-Bit, True Output, TTL, CQCC28, QFN-28

SNJ54AS866FK规格参数

参数名称属性值
厂商名称Rochester Electronics
包装说明QCCN,
Reach Compliance Codeunknown
其他特性OPEN COLLECTOR A = B OUTPUT; ARITHMETIC COMPARISON; CASCADABLE; OUTPUT LATCH
系列AS
JESD-30 代码S-CQCC-N28
长度11.43 mm
逻辑集成电路类型MAGNITUDE COMPARATOR
位数8
功能数量1
端子数量28
最高工作温度125 °C
最低工作温度-55 °C
输出极性TRUE
封装主体材料CERAMIC, METAL-SEALED COFIRED
封装代码QCCN
封装形状SQUARE
封装形式CHIP CARRIER
传播延迟(tpd)17 ns
座面最大高度2.03 mm
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术TTL
温度等级MILITARY
端子形式NO LEAD
端子节距1.27 mm
端子位置QUAD
宽度11.43 mm

SNJ54AS866FK文档预览

SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
Package Options Include Plastic Small
Outline Packages, Both Plastic and Ceramic
Chip Carriers, and Standard Plastic and
Ceramic DIPs
Input and Output Latches with Active-High
Enables
Fast Compare to Zero
Arithmetic and Logical Comparison
Open-Collector P = Q Output
SN54AS866 . . . JD PACKAGE
SN74AS866A . . . N PACKAGE
(TOP VIEW)
description
These Advanced Schottky devices are capable of
performing high-speed arithmetic or logical
comparisons on two 8-bit binary or two’s
complement words. Three fully decoded
decisions about words P and Q are externally
available at the outputs. These devices are fully
expandable to any word length by connecting the
totem pole P>Q and P<Q outputs of each stage to
the P>Q and P<Q inputs of the next higher-order
stage. The cascading paths are implemented with
only a two-gate-level delay to reduce overall
comparison times for long words. The open-
collector P=Q output may be wire-ANDed
together.
Both input words P and Q plus all three outputs
(P>Q, P<Q, and P = Q) are equipped with latches
to provide the designer with temporary data
storage for avoiding race conditions. The enable
circuitry is implemented with minimal delay times
to enhance performance when the devices are
cascaded for longer word lengths. Each latch is
transparent when the appropriate latch enable,
PLE, QLE, or OLE is high.
The enable inputs PLE and QLE and data inputs
P and Q utilize pnp input transistors to reduce the
low-level input current requirement to typically
– 0.25 mA, which minimizes loading effects.
QLE
L/A
p < Qin
P > Qin
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
P = Qout
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
CLRQ
PLE
P7
P6
P5
P4
P3
P2
P1
P0
P < Qout
P > Qout
OLE
SN54AS866 . . . FK PACKAGE
SN74AS866A . . . FN PACKAGE
(TOP VIEW)
P > Qin
P < Qin
L/A
QLE
VCC
CLRQ
PLE
Q7
Q6
Q5
Q4
Q3
Q2
Q1
5
6
7
8
9
10
4
3 2 1 28 27 26
25
24
23
22
21
20
11
19
12 13 14 15 16 17 18
P7
P6
P5
P4
P3
P2
P1
The Q register may be cleared to zero for a fast comparison of the P word to zero.
The SN54AS866 is characterized for operation over the full military temperature range of – 55°C to 125°C. The
SN74AS866A is characterized for operation from 0°C to 70°C.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Q0
P = Qout
GND
OLE
P > Qout
P < Qout
P0
Copyright
©
1990, Texas Instruments Incorporated
1
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
logic symbol
L/A
PLE
PO
P1
P2
P3
P4
P5
P6
P7
P>Q
P<Q
QLE
CLR Q
QLE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
26
18
19
20
21
22
23
24
25
4
3
15
27
1
12
11
10
9
8
7
6
5
COMP
M [LOGIC]
M [ARITH, 2s COMP]
C1
1D
1=0 0
P
C3
R
C2
2D
7
P > Q 3D
P < Q 3D
P = Q 3D
16
17
13
P>Q
P<Q
P=Q
1=0 0
Q
7
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
logic diagram (positive logic)
15
OLE
26
P7=Q7
C1
25
1D
P7
P7
24
P6
P6
23
P5
P5
22
P4
P4
21
P3
P3
20
P2
P2
19
P1
P1
18
P0
P0
P0=Q0
P1=Q1
P2=Q2
C1
1D
17
16
13
P3=Q3
P5=Q5
P6=Q6
PLE
P7
P6
P3
P4
P3
P2
P1
P<Q
P>Q
P=Q
P0
CLRQ
1
QLE
5
27
R
C1
1D
Q7
Q7
6
Q6
Q6
7
Q5
Q5
8
Q4
Q4
9
Q3
Q3
10
Q2
Q2
11
Q1
Q1
12
Q0
Q0
4MSB=
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
4
P>QIN
3
P<1I
2
L/A
Arith
Logic
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
3
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
FUNCTION TABLE
COMPARISON
Logical
Logical
Logical
Logical
Logical
Logical
Arithmetic
Arithmetic
Arithmetic
Arithmetic
Arithmetic
Arithmetic
L/A
H
H
H
H
H
H
L
L
L
L
L
L
DATA INPUTS
P0 – P7, Q0 – Q7
P>Q
P<Q
P=Q
P=Q
P=Q
P=Q
P AG Q
Q AG P
P=Q
P=Q
P=Q
P=Q
INPUTS
P>Q
X
X
L
L
H
H
X
X
L
L
H
H
P<Q
X
X
L
H
L
H
X
X
L
H
L
H
P>Q
H
L
L
L
H
H
H
L
L
L
H
H
OUTPUTS
P<Q
L
H
L
H
L
H
L
H
L
H
L
H
P=Q
L
L
H
L
L
L
L
L
H
L
L
L
AG = arithmetically greater than
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Off-state output voltage, P = Q output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Operating free-air temperature range: SN54AS866 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
SN74AS866A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
recommended operating conditions
SN54AS866
MIN
VCC
VIH
VIL
IOH
VOH
IOL
tsu
th
tA
Supply voltage
High-level input voltage
Low-level input voltage
High-level output current, all outputs except P=Q
High-level output voltage, P=Q output
Low-level output current
Setup time to PLE, OLE, OLE↓
Hold time after PLE, QLE, OLE↓
Operating free-air temperature
2
4
– 55
125
4.5
2
0.8
–2
5.5
20
2
4
0
70
°C
NOM
5
MAX
5.5
SN74AS866A
MIN
4.5
2
0.8
–2
5.5
20
NOM
5
MAX
5.5
UNIT
V
V
V
mA
V
mA
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
SN54AS866, SN74AS866A
8-BIT MAGNITUDE COMPARATORS
SDAS183A – DECEMBER 1982 – REVISED JUNE 1990
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
IOH
VOL
II
IIH
L/A, OLE
Others
L/A, OLE,
P>Qin,
IIL
P<Qin
CLRQ
P, Q, PLE, QLE
IO‡
ICC
NOTE 1: ICC is measured with all inputs high except L/A, which is low.
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.25 V
See Note 1
– 20
160
– 0.25
VCC = 5.5 V,
VI = 0.4 V
–2
–1
– 112
240
– 20
160
– 0.25
– 112
240
mA
mA
–2
–4
–4
mA
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V to 5.5 V,
VCC = 4.5 V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5 5 V
5.5 V,
II = – 18 mA
IOH = – 2 mA
VOH = 5.5 V
IOL = 20 mA
VI = 7 V
VI = 2 7 V
2.7
SN54AS866
MIN
TYP†
MAX
– 1.2
VCC – 2
0.25
0.35
0.5
0.1
40
20
0.35
VCC – 2
0.25
0.5
0.1
40
20
mA
V
mA
µA
SN74AS866A
MIN
TYP†
MAX
– 1.2
UNIT
V
P>Q, P<Q
P=Q only
switching characteristics (see Note 2
VCC = 4.5 V to 5.5 V,
,
CL = 50 pF,
p ,
RL = 500
Ω,
TA = MIN to MAX§
SN54AS866
SN74AS866A
MIN TYP†
MAX
MIN TYP†
MAX
1
1
1
P<Q, P>Q
,
Any P or Q
y
Data Input
CLRQ
1
1
1
1
1
8.5
7.5
5
5.5
13.5
10
16
12
14
14
10
10
21
17
21
17
1
1
1
1
1
1
1
1
8.5
7
5
5.5
13.5
10
16
12
19
13
8
8
17.5
15
20
16
PARAMETER
FROM
(
)
(INPUT)
TO
(
)
(OUTPUT)
UNIT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
L/A
P<Q,
P<Q P>Q
ns
ns
ns
ns
PARAMETER
FROM
(
)
(INPUT)
TO
(
)
(OUTPUT)
VCC = 4.5 V to 5.5 V,
pF,
CL = 50 p ,
RL = 280
Ω,
TA = MIN to MAX§
SN54AS866
SN74AS866A
MIN TYP
MAX
MIN TYP†
MAX
1
1
1
1
1
1
6.5
8
10
9
12
13
12
14
15
14
17
18
1
1
1
1
1
1
6.5
8
10
9
12
13
16
14
17
14
24
21
UNIT
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
P<Q,
P>Q
Any P or Q
y
Data Input
CLRQ
P=Q
P=Q
P=Q
ns
ns
ns
† All typical values are at VCC = 5 V, TA = 25°C.
‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit, IOS.
§ For conditions shown MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuit and voltage waveforms are shown in Section 1 of the
ALS/AS Logic Data Book,
1986.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
5

SNJ54AS866FK相似产品对比

SNJ54AS866FK
描述 Magnitude Comparator, AS Series, 8-Bit, True Output, TTL, CQCC28, QFN-28
厂商名称 Rochester Electronics
包装说明 QCCN,
Reach Compliance Code unknown
其他特性 OPEN COLLECTOR A = B OUTPUT; ARITHMETIC COMPARISON; CASCADABLE; OUTPUT LATCH
系列 AS
JESD-30 代码 S-CQCC-N28
长度 11.43 mm
逻辑集成电路类型 MAGNITUDE COMPARATOR
位数 8
功能数量 1
端子数量 28
最高工作温度 125 °C
最低工作温度 -55 °C
输出极性 TRUE
封装主体材料 CERAMIC, METAL-SEALED COFIRED
封装代码 QCCN
封装形状 SQUARE
封装形式 CHIP CARRIER
传播延迟(tpd) 17 ns
座面最大高度 2.03 mm
最大供电电压 (Vsup) 5.5 V
最小供电电压 (Vsup) 4.5 V
标称供电电压 (Vsup) 5 V
表面贴装 YES
技术 TTL
温度等级 MILITARY
端子形式 NO LEAD
端子节距 1.27 mm
端子位置 QUAD
宽度 11.43 mm
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