FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Connection Diagrams
27C040
27C010 27C512
XX/VPP XX/VPP
A16
A16
A15
A15
A12
A12
A7
A7
A6
A6
A5
A5
A4
A4
A3
A3
A2
A2
A1
A1
A0
A0
O0
O0
O1
O1
O2
O2
GND
GND
DlP
FM27C256
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
27C512
27C010
27C040
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
VCC
XX/PGM
A18
VCC
V
CC
XX
A17
A14
A14
A14
A14
A13
A13
A13
A13
A8
A8
A8
A8
A9
A9
A9
A9
A11
A11
A11
A11
OE/VPP
OE
OE
OE
A10
A10
A10
A10
CE/PGM
CE/PGM
CE
CE/PGM
O7
O7
O7
O7
O6
O6
O6
O6
O5
O5
O5
O5
O4
O4
O4
O4
O3
O3
O3
O3
DS800034-2
Note:
Compatible EPROM pin configurations are shown in the blocks adjacent to the FM27C256 pins.
Commercial Temp. Range (0
°
C to +70
°
C)
V
CC
= 5V
±
10%
Parameter/Order Number
FM27C256 Q, N, V 90
FM27C256 Q, N, V 120
FM27C256 Q, N, V 150
Pin Names
Symbol
A0–A14
CE/PGM
OE
O0–O7
XX
Description
Addresses
Chip Enable/Program
Output Enable
Outputs
Don’t Care (during Read)
Access Time (ns)
90
120
150
Extended Temp. Range (-40
°
C to +85
°
C)
V
CC
= 5V
±
10%
Parameter/Order Number
FM27C256 QE, NE, VE 120
FM27C256 QE, NE, VE 150
PLCC
A
7
A
12
V
PP
XX
V
CC
A
14
A
13
4
3
2
1 32 31 30
Access Time (ns)
120
150
Note:
Surface mount PLCC package available for commercial and extended
temperature ranges only.
Package Types: FM27C256 Q, N, V XXX
Q = Quartz-Windowed Ceramic DIP
N = Plastic OTP DIP
V = Surface-Mount PLCC
• All Packages conform to the JEDEC standard.
• All versions are guaranteed to function for slower speeds.
A
6
A
5
A
4
A
3
A
2
A
1
A
0
XX
O
0
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20
29
28
27
26
25
24
23
22
21
A
8
A
9
A
11
XX
OE
A
10
CE/PGM
O
7
O
6
O
1
O
2
GND
XX
O
3
O
4
O
5
DS800034-3
Top
2
FM27C256
www.fairchildsemi.com
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Absolute Maximum Ratings
(Note 1)
Storage Temperature
All Input Voltages except A9 with
Respect to Ground
V
PP
and A9 with Respect
to Ground
V
CC
Supply Voltage with
Respect to Ground
-65°C to +150°C
-0.6V to +7V
-0.7V to +14V
-0.6V to +7V
ESD Protection
All Output Voltages with
Respect to Ground
> 2000V
V
CC
+ 1.0V to GND -0.6V
Operating Range
Range
Comm’l
Industrial
Temperature
0°C to +70°C
-40°C to +85°C
V
CC
+5V
±10%
+5V
±10%
Read Operation
DC Electrical Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
V
IL
V
IH
V
OL
V
OH
I
SB1
(Note 11)
I
SB2
I
CC1
I
PP
V
PP
I
LI
I
LO
Parameter
Input Low Level
Input High Level
Output Low Voltage
Output High Voltage
V
CC
Standby Current
(CMOS)
V
CC
Standby Current (TTL)
V
CC
Active Current
TTL Inputs
V
PP
Supply Current
V
PP
Read Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min
-0.5
2.0
Max
0.8
V
CC
+1
0.4
Units
V
V
V
V
I
OL
= 2.1 mA
I
OH
= -2.5 mA
CE = V
CC
±0.3V
CE = V
IH
CE = OE = V
IL
,f=5 MHz
Inputs = V
IH
or V
IL
, I/O = 0 mA
V
PP
= V
CC
V
CC
- 0.7
V
IN
= 5.5V or GND
V
OUT
= 5.5V or GND
-1
-10
3.5
100
1
35
10
V
CC
1
10
µA
mA
mA
µA
V
µA
µA
AC Electrical Characteristics
Over Operating Range with V
PP
= V
CC
Symbol
t
ACC
t
CE
t
OE
t
DF
(Note 2)
t
OH
(Note 2)
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
Output Disable to
Output Float
Output Hold from
Addresses,
CE or OE, Whichever
Occurred First
90
100
120
150
200
Units
Min Max Min Max Min Max Min Max Min Max
90
90
35
30
0
0
100
100
50
30
0
120
120
50
35
0
150
150
50
45
0
200
200
50
45
ns
Capacitance
(Note 2) T
A
= +25˚C, f = 1 MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ Max Units
V
IN
= 0V
V
OUT
= 0V
6
9
12
12
pF
pF
3
FM27C256
www.fairchildsemi.com
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
AC Test Conditions
Output Load
1 TTL Gate and CL = 100 pF (Note 8)
≤
5 ns
0.45 to 2.4V
Input Rise and Fall Times
Input Pulse Levels
Timing Measurement Reference Level (Note 10)
Inputs
0.8V and 2.0V
Outputs
0.8V and 2.0V
AC Waveforms
(Note 6) (Note 7) (Note 9)
ADDRESSES
2.0V
0.8V
ADDRESSES VALID
CE
2.0V
0.8V
t
CE
t
CE
(Notes 4, 5)
OE
2.0V
0.8V
t
OE
(Note 3)
t
DF
(Notes 4, 5)
OUTPUT
2.0V
0.8V
Hi-Z
ACC
(Note 3)
VALID OUTPUT
t
t
OH
Hi-Z
DS800034-4
Note 1:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2:
This parameter is only sampled and is not 100% tested.
Note 3:
OE may be delayed up to t
ACC
- t
OE
after the falling edge of CE without impacting t
ACC
.
Note 4:
The t
DF
and t
CF
compare level is determined as follows:
High to TRI-STATE
®
, the measured V
OH1
(DC) - 0.10V;
Low to TRI-STATE, the measured V
OL1
(DC) + 0.10V.
Note 5:
TRI-STATE may be attained using OE or CE.
Note 6:
The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1
µF
ceramic capacitor be used on every device
between V
CC
and GND.
Note 7:
The outputs must be restricted to V
CC
+ 1.0V to avoid latch-up and device damage.
Note 8:
TTL Gate: I
OL
= 1.6 mA, I
OH
= -400
µA.
C
L
= 100 pF includes fixture capacitance.
Note 9:
V
PP
may be connected to V
CC
except during programming.
Note 10:
Inputs and outputs can undershoot to -2.0V for 20 ns Max.
Note 11:
CMOS inputs: V
IL
= GND
±0.3V,
V
IH
= V
CC
±0.3V.
4
FM27C256
www.fairchildsemi.com
FM27C256 262,144-Bit (32K x 8) High Performance CMOS EPROM
Programming Characteristics
(Note 12) (Note 13) (Note 14) (Note 15)
Symbol
t
AS
t
OES
t
VPS
t
VCS
t
DS
t
AH
t
DH
t
DF
t
PW
t
OE
I
PP
I
CC
T
A
V
CC
V
PP
t
FR
V
IL
V
IH
t
IN
t
OUT
Parameter
Address Setup Time
OE Setup Time
V
PP
Setup Time
V
CC
Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Output Enable to Output
Float Delay
Program Pulse Width
Data Valid from OE
V
PP
Supply Current
during Programming Pulse
V
CC
Supply Current
Temperature Ambient
Power Supply Voltage
Programming Supply Voltage
Input Rise, Fall Time
Input Low Voltage
Input High Voltage
Input Timing Reference Voltage
Output Timing Reference Voltage
Conditions
Min
1
1
1
1
1
0
1
Typ
Max
Units
µs
µs
µs
µs
µs
µs
µs
CE = V
IL
0
45
50
60
105
100
30
50
ns
µs
ns
mA
mA
°C
V
V
ns
CE = V
IL
CE = V
IL
20
6.25
12.5
5
25
6.5
12.75
30
6.75
13.0
0.0
2.4
0.8
0.8
4.0
0.45
V
V
2.0
2.0
V
V
Programming Waveforms
(Note 14)
PROGRAM
PROGRAM
VERIFY
ADDRESSES
2.0V
0.8V
t
AS
ADDRESS N
t
AH
DATA IN STABLE
ADD N
t
DS
t
DH
DATA OUT VALID
ADD N
t
DF
DATA
2.0V
0.8V
V
CC
5.25V
t
VCS
V
PP
12.75V
t
VPS
2.0V
0.8V
t
OES
t
PW
t
OE
CE
OE
2.0V
0.8V
DS800034-5
Note 12:
Fairchild’s standard product warranty applies to devices programmed to specifications described herein.
Note 13:
V
CC
must be applied simultaneously or before V
PP
and removed simultaneously or after V
PP
. The EPROM must not be inserted into or removed from a board with
voltage applied to V
PP
or V
CC
.
Note 14:
The maximum absolute allowable voltage which may be applied to the V
PP
pin during programming is 14V. Care must be taken when switching the V
PP
supply to
prevent any overshoot from exceeding this 14V maximum specification. At least a 0.1
µF
capacitor is required across V
PP
, V
CC
to GND to suppress spurious voltage transients
which may damage the device.
Note 15:
During power up the PGM pin must be brought high (≥ V
IH
) either coincident with or before power is applied to V
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