VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7122
Features
• Supports ANSI X3T11 1.0625 Gbit/sec
FC-AL Disk Attach for Resiliency
• Fully Differential for Minimum
Jitter Accumulation.
• Quad PBC’s in Single Package
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
• TTL Bypass Select
• High Speed, PECL I/O’s Referenced to V
DD
.
• 0.35W Typical Power Dissipation
• 3.3V Power Supply
• 44-Pin, 10mm PQFP
General Description
The VSC7122 is a Quad Port Bypass Circuit (PBC). Four Fibre Channel PBC’s are cascaded into a single
part to minimize part count, cost, high frequency routing, and jitter accumulation. Port Bypass Circuits are used
to provide resiliency in Fibre Channel Arbitrated Loop (FC-AL) architectures. PBC’s are used within FC-AL
disk arrays to allow for resiliency and hot swapping of FC-AL drives.
A Port Bypass Circuit is a 2:1 Multiplexer with two modes of operation: NORMAL and BYPASS. In NOR-
MAL mode, the disk drive is connected to the loop. Data goes from the 7122’s L_SOn pin to the Disk Drive RX
input and data from the disk drive TX output goes to the 7122’s L_SIn pin. Refer to Figure 2 for disk drive
application. In BYPASS mode, the disk drive is either absent or non-functional and data bypasses to the next
available disk drive. Normal mode is enabled with a HIGH on the SEL pin and BYPASS mode is enabled by a
LOW on the SEL pin. Direct Attach Fibre Channel Disk Drives have an “LRC Interlock” signal defined to con-
trol the SEL function.
Using a VSC7122 in a single loop of a disk array is illustrated in Figure 2: “Disk Array Application”. FC-
AL drives are all expected to be dual loop. The VSC7122 is cascaded in a manner such that all the 7122’s inter-
nal PBC’s are used in the same loop. For dual loop implementations, two or more VSC7122’s should be used.
Allocating each VSC7122 to only one of two loops preserves redundancy, prevents a single point of failure and
lends itself to on-line maintainability.
The VSC7122 is very similar to the VSC7121 except that LSO+ outputs are all full power outputs identical
to OUT. This is useful in passive backplanes to provide additional amplitude on long traces.
7122 Block Diagram
LSO1+
LSO1-
LSO2+
LSO2-
LSO3+
LSO3-
LSO4+
LSO4-
LSI1+
LSI1-
LSI2+
LSI2-
LSI3+
LSI3-
LSI4+
LSI4-
SEL1
SEL2
SEL3
SEL4
1
0
OUT+
OUT-
1
IN+
IN-
0
1
0
1
0
PBC1
PBC2
PBC3
PBC4
G52155-0, Rev. 2.1
8/31/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
The VSC7122 can be cascaded through the IN and OUT pins for arrays of disk drives greater than 4. For
disk arrays with a noninteger multiple of 4 disk drives, the unused PBC’s can be hardwired to bypass with a
external pulldown resistor.
Table 1 is a truth table detailing the data flow through the VSC7122. Figure 1 shows a timing diagram of the
data relationship in the VSC7122. There are no critical timing (setup, hold, or delay) parameters for the
VSC7122 as this part routes the serial data encoded with the baud clock that is extracted by a Fibre Channel
receiver. The primary AC parameter of importance is the jitter or data eye degradation inserted by the port
bypass circuit. The design of the VSC7122 minimizes jitter accummulation by using fully differential circuits.
This provides for symmetric rise and fall delays as well as noise rejection.
Table 1: Truth Table
SELECT STATE
SEL1
L
L
L
L
H
H
DATA OUTPUTS
SEL4
L
H
L
L
L
H
SEL2
L
L
L
H
L
H
SEL3
L
L
H
L
L
H
OUT
IN
SI4
SI3
SI2
SI1
SI4
SO4
IN
IN
SI3
SI2
SI1
SI3
SO3
IN
IN
IN
SI2
SI1
SI2
SO2
IN
IN
IN
IN
SI1
SI1
SO1
IN
IN
IN
IN
IN
IN
Figure 1: Timing Waveforms
IN+/-
LSI1+/-
LSI2+/-
LSI3+/-
LSI4+/-
OUT+/-
LSO1+/-
LSO2+/-
LSO3+/-
LSO4+/-
T
1
T
2
T
jitter
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7122
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Figure 2: Disk Array Application
7120
VSC7122 QUAD PORT BYPASS CIRCUIT
Dual SC
or
DB-9
Optics
or
Copper
7120
normal
LRC Interlock
FC-AL DISK DRIVE
0
1
TX
E_STORE
RX
normal
LRC Interlock
FC-AL DISK DRIVE
0
1
TX
E_STORE
RX
bypass
0
1
Pulldown for Bypass
in Absense of Disk Drive
normal
0
LRC Interlock
FC-AL DISK DRIVE
1
TX
E_STORE
RX
JBOD
G52155-0, Rev. 2.1
8/31/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Advance Product Information
VSC7122
Table 2: AC Characteristics
(Over recommended operating conditions).
Parameters
T
1
T
2
T
SDR
, T
SDF
Description
Flow-Through Propagation Delay
Rising Edge to Rising Edge
Flow through Propagation Delay
Falling Edge to Falling Edge
Serial data rise and fall time
Min.
Max.
7.0
7.0
Units
ns
ns
ps.
Conditions
Delay with all circuits bypassed. 75
Ohm Load
Delay with all circuits bypassed. 75
Ohm load.
20% to 80%, tested on a sample basis
—
300
Table 3: DC Characteristics
(Over recommended operating conditions).
Parameters
Description
Min
Typ
Max
Units
Conditions
V
IH(TTL)
V
IL(TTL)
I
IH(TTL)
I
IL(TTL)
V
DD
I
DD
P
D
∆
V
IN
∆
V
OUT50
∆
V
OUT75
Input HIGH voltage (SEL - TTL)
Input LOW voltage (SEL - TTL)
Input HIGH current (SEL- TTL)
Input LOW current (SEL - TTL)
Supply voltage
Supply current
Power Dissipation
Receiver differential peak-to-peak
Input Sensitivity, IN+/- & L_SIn+/-
Output differential peak-to-peak
voltage swing
Output differential peak-to-peak
voltage swing
2.0
0
—
—
3.10
—
—
—
50
—
—
—
0.35
5.5
0.8
500
-500
3.50
150
0.5
2600
V
V
µ
A
µ
A
V
mA
W
mVp-p
mVp-p
mVp-p
I
IH
< 6.6 mA @ V
IH
= 5.5 V
—
V
IN
= 2.4 V
V
IN
= 0.5 V
V
DD
= 3.30V + 5%
Outputs open, V
DD
= V
DD
max
Outputs open, V
DD
= V
DD
max
AC Coupled.
Internally biased at V
DD
/2
50
Ω
to V
DD
– 2.0 V
75
Ω
to V
DD
– 2.0 V
300
1000
1200
—
2200
2200
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52155-0, Rev. 2.1
8/31/98
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7122
Absolute Maximum Ratings
(1)
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
TTL Power Supply Voltage, (V
DD
) ..................................................................................................... 0.5V to +4V
PECL DC Input Voltage, (V
INP
)............................................................................................. -0.5V to V
DD
+0.5V
TTL DC Input Voltage, (V
INT
) ..........................................................................................................-0.5V to 5.5V
DC Voltage Applied to Outputs for High Output State, (V
IN TTL
)........................................ -0.5V to V
DD
+ 0.5V
TTL Output Current (I
OUT
), (DC, Output High)........................................................................................... 50mA
PECL Output Current, (I
OUT
), (DC, Output High) ......................................................................................-50mA
Case Temperature Under Bias, (T
C
)............................................................................................... -55
°
to +125
o
C
Storage Temperature, (T
STG
)......................................................................................................... -65
°
to + 150
o
C
Maximum Input ESD .................................................................................................................................. 1500 V
Recommended Operating Conditions
(2)
Power Supply Voltage, (V
DD
) ...........................................................................................................+3.1V to 3.5V
Ambient Operating Temperature Range, (T) .....................................................................................0
°
C to +70
°
C
Notes:
1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without causing per-
manent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may
affect device reliability.
2) Vitesse guarantees the functional and parametric operation of the part under “Recommended Operating Conditions: except
where specifically noted in the AC and DC Parametric Tables
G52155-0, Rev. 2.1
8/31/98
©
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5
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