VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
Features
• Integrated
TIA and Limiting Amplifier
• Low Power Consumption for SFF Applications
• TO Package-Compatible Layout
• On-Chip Signal Detect
• On-Chip Linear Photocurrent Monitor
• Single 3.3V Supply
• 5V Supply Operation via Wirebond Option
• Compatible with PIN or Avalanche Detectors
• Packages: 16-Pin TSSOP, TO-46, Bare Die
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Applications
• 2.488Gb/s, 3.125Gb/s SONET OC-48/
SDH STM-16
• 2.125Gb/s Fibre Channel
• 2.5Gb/s or 3.125Gb/s Ethernet Applications with
8B/10B Overhead
• SFF Transceivers
General Description
The VSC7969 is a 3.125Gb/s transimpedance amplifier IC with a built-in limiting amplifier, a signal detect
feature and a photocurrent monitor. The VSC7969 does not require any external electrical components in the
construction of a high performance optical receiver such as for SONET/SDH applications. The analog output is
a differential signal with a minimum amplitude of 200mVp-p (single-ended). The VSC7969 operates with a sin-
gle power supply with a maximum power dissipation of 300mW. A PIN photodiode or APD can be connected
and separately biased to provide optimal performance.
The VSC7969 provides filtered bias for MSM and PIN photodetectors; applications using an APD photode-
tector must supply bias separately. The VSC7969 also provides a photocurrent monitor whose output is linearly
proportional to the input photocurrent.
The VSC7969 can operate from a single +3.3V supply or a +5V or -5.2V supply. The VSC7969 is offered
in die form and in a 16-pin plastic thin-shrink small outline package (TSSOP-16). A fully tested TO-46 outline
packaged receiver with a photodetector is also available.
Block Diagram
VCCS
Filter
+3.3V
Regulator
+5V
+3.3V
VCCD
GND
Dual power supply pins are
provided for +5V or +3.3V
operation. Only one power
supply pin should be connected.
50Ω
In
50Ω
VOUTP
VOUTN
Signal
Detect
Outputs need to
be AC-coupled
0.1µF
0.1µF
SD_OUT
SD_ADJ
VSC7969
Monitor
IMON
G52355-0, Rev 2.0
02/09/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Advance Product Information
VSC7969
Electrical Characteristics
Table 1: AC Specifications
Symbol
∆I
PH
I
PHS-AVG
Parameter
Input Photocurrent Swing
Min
Typ
Max
2.2
Units
mA
Conditions
Peak-to-peak AC current
amplitude
-23dBm average optical power
with a detector responsitivity of
0.8A/W.
-23dBm average optical power
with a detector responsitivity of
0.8A/W.
Single-ended peak-to-peak
measurement, I
IN
>20µA.
Differential peak-to-peak
measurement, I
IN
>20µA.
At 2.2mAp-p input photocurrent
swing. 20% to 80%.
Differential measurement
Modulation frequency between F
L
and BW
Referenced to 10MHz,
CPD = 0.6pF
Referenced to 10MHz, CPD =
0.6pF with no external
components
Single-ended
30kHz to 2.5GHz
Bias voltage on detector at 2.0V
Electrical measurement on SD pin
Average photocurrent with SD
open.
Average photocurrent with SD
open.
Average photocurrent with SD
shorted to ground.
Average photocurrent with SD
shorted to ground.
Average Photocurrent Sensitivity
4
µA
I
PHS-PEAK
∆V
OUT-SE
∆V
OUT-DIFF
t
R
, t
F
Z
T(1)
∆Z
T(1)
BW
Peak Input Photocurrent Sensitivity
Single-Ended Output Voltage
Amplitude
Differential Output Voltage Amplitude
Rise and Fall Time
Transimpedance Gain
Ripple in Passband Transimpedance
Upper -3dB Bandwidth
2.2
20k
8
µA
200
400
250
500
60
27k
1
2.5
300
600
100
40k
mV
mV
ps
Ω
dB
3.0
GHz
F
L
Z
O
PSRR
I
NOISE
C
PD
SD
H
SD
A-OPEN
SD
D-OPEN
SD
A-SHORT
SD
D-SHORT
SD
HIGH
SD
LOW
Lower -3dB Cutoff Frequency
Output Impedance
Power Supply Rejection Ratio
Input-Referred rms Noise Current
Photodetector Capacitance
Signal Detect Hysterisis
Signal Detect Assertion Level
Signal Detect Deasseration Level
Signal Detect Asseration Level
Signal Detect Deasseration Level
Signal Detect HIGH Logic Level
Signal Detect LOW Logic Level
0.4
1
3
1.0
6
2.0
50
TBD
500
0.6
2
5
2.2
10
4.4
V
CCS
- 0.3
0.5
100
kHz
Ω
nA
0.8
4
9
3.0
18
6.0
pF
dB
µA
µA
µA
µA
V
0.8
V
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52355-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
Symbol
MON
DC
IMON
RANGE
R
J
D
J
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Min
Typ
0.8
-5
5
0
TBD
TBD
+5
200
10
Parameter
Slope of Linear Analog Photocurrent
Monitor vs Input Optical Power
Duty Cycle
Photocurrent Monitor Linearity Range
Random Jitter
(2)
Deterministic Jitter
(3)
Max
Units
µA/µW
%
µA
µA
ps
ps
Conditions
0Ω to 2kΩ to V
CC
with a detector
responsitivity of 0.8A/W
IMON
OFFSET
Photocurrent Monitor Offset
Peak-to-peak
Peak-to-peak
NOTES: (1) The transimpedance gain is defined as Z
T
= (∆V
OUT - DIFF
)/∆I
PH
. (2) Using 1111100000 pattern at 2.5Gb/s to measure the
standard deviation of the edge of the pattern, multiply the standard deviation by 14 to achieve the total random jitter. (3) +K28.5
- K28.5 (00111110101100000101).
Table 2: DC Specifications
Symbol
GND
V
CCS
V
CCD
ICC
V
OUT-CM
V
ANODE
V
CATHODE
V
CAT-EXT
V
APD
Parameter
Negative Supply Rail
Positive Supply Rail for 3.3V Operation
Positive Supply Rail for 5V Operation
Power Supply Current
Common-Mode Voltage on Output Pins
Internal DC Bias Voltage on Detector
Anode Contact
Interal DC Bias Voltage on Detector
Cathode Contact
External DC Bias Voltage Permissable
on Detector Cathode Contact
External DC Bias Voltage for Use with
Avalanche Photodetector
Min
3.0
4.5
Typ
0
3.3
5.0
65
V
CCS
-
125mV
Max
3.6
5.5
75
Units
V
V
V
mA
Conditions
3.3V
Applicable to VOUTP and
VOUTN pins at 50Ω load.
0.8
V
CCS
-
0.15V
0.9
1.0
V
CCS
V
V
V
V
3.3
60
10
Absolute Maximum Ratings
(1)
(at T
A
= +25
°
C, unless otherwise specified)
Power Supply Voltage (V
CCS
)......................................................................................................................... 3.6V
Power Supply Voltage (V
CCD
) ........................................................................................................................ 5.5V
Junction Temperature Range ........................................................................................................ -40°C to +125°C
Storage Temperature Range ......................................................................................................... -40°C to +125°C
Relative Ambient Humidity ................................................................................................................. 85%/+85°C
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Supply (V
CCS
) ...................................................................................................................... 3.3V
Positive Voltage Supply (V
CCD
)...................................................................................................................... 5.0V
Negative Voltage Rail (GND) ............................................................................................................................ 0V
Ambient Temperature Range (T
A
)
(1)
.............................................................................................. -40°C to +85°C
G52355-0, Rev 2.0
02/09/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Advance Product Information
VSC7969
Bare Die Descriptions
Figure 1: Pad Assignments
1467µm (57.2mil)
Pad 6
VOUTN
Pad 5
SD_ADJ
Pad 4
SD_TP
Pad 7
SD_OUT
Pad 8
GND
Pad 9
VOUTN
Pad 10
GND
Pad 11
VOUTP
Pad 12
GND
Pad 13
IMON
Pad 14
VOUTP
Pad 15
GND
Pad 16
CSDN
1143µm
(45.0mil)
Pad 3
GND
Pad 2
BG_VREF
Pad 1
GND
Pad 26
VCCD
Pad 25
VCCS
Pad 24
GND
VSC7969
Pad 17
CSDP
Pad 18
GND
Pad 19
GND
Pad 23
IN
Pad 22
FILTER
Pad 21
GND
Pad 20
GND
Die Size: 1143µm x 1453µm (45.0mil x 57.2mil)
Die Thickness: 279
µm (11.0mil)
Pad Size:
100µm x 100µm (3.9mil x 3.9mil)
Pad Passivation Opening:
86µm x 86µm (3.4mil x 3.4mil)
Scribe Size: 143µm (5.6mil)
143µm
(5.6mil)
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52355-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7969
Table 3: Pad Coordinates
Signal
Name
GND
BG_VREF
GND
SD_TP
SD_ADJ
VOUTN
SD_OUT
GND
VOUTN
GND
VOUTP
GND
IMON
VOUTP
GMD
CSDN
CSDP
GND
GND
GND
GND
FILTER
IN
GND
VCCS
VCCD
3.125Gb/s Integrated Transimpedance
and Limiting Amplifier with Signal Detect
Pad
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Coordinates (µm)
Description
X
130
130
130
130
130
137
280
405
530
655
780
905
1030
1173
1180
1180
1180
1180
1180
1030
905
780
530
405
280
137
Y
250
375
500
625
750
875
875
875
875
875
875
875
875
875
750
625
500
375
250
125
125
125
125
125
125
125
Negative power supply rail (typically 0V)
Band Gap voltage reference 1.24V for testpoint, no connect
Negative power supply rail (typically 0V)
Signal Detect test point, DO NOT CONNECT.
Signal Detect threshold adjustment (see
Application amd Usage
section)
Complementary logic output (logic LOW when photocurrent is
HIGH)
Signal detect output (logic HIGH when photocurrent exceeds
SD
A
)
Negative power supply rail (typically 0V)
Complementary logic output (logic LOW when photocurrent is
HIGH)
Negative power supply rail (typically 0V)
Positive logic output (logic HIGH when photocurrent is HIGH)
Negative power supply rail (typically 0V)
Photocurrent Monitor
Positive logic output (logic HIGH when photocurrent is HIGH)
Negative power supply rail (typically 0V)
Test point for Signal Detect capacitor. DO NOT CONNECT.
Test point for Signal Detect capacitor. DO NOT CONNECT.
Negative power supply rail (typically 0V)
Negative power supply rail (typically 0V)
Negative power supply rail (typically 0V)
Negative power supply rail (typically 0V)
Photodetector cathode connection (filtered V
CC
)
Photodetector anode connection
Negative power supply rail (typically 0V)
Positive power supply rail for 3.3V operation
Positive power supply rail for 5V operation
G52355-0, Rev 2.0
02/09/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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