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MAS8251LL: 产品描述Telecom IC,; 产品类别无线/射频/通信电信电路; 文件大小326KB，共23页; 制造商Microsemi; 官网地址https://www.microsemi.com

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MAS8251LL概述

Telecom IC,

MAS8251LL规格参数

参数名称	属性值
厂商名称	Microsemi
包装说明	,
Reach Compliance Code	compliant

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THIS DOCUMENT IS FOR MAINTENANCE

PURPOSES ONLY AND IS NOT

RECOMMENDED FOR NEW DESIGNS

APRIL 1995

MA8251

DS3810-2.4

MA8251

RADIATION HARD PROGRAMMABLE

COMMUNICATION INTERFACE

The MA8251 is based on the industry standard 8251A

Universal Synchronous Asynchronous Receiver/Transmitter

(USART).

The MA8251 is used as a peripheral device and is

programmed by the CPU to operate using virtually any serial

data transmission technique presently in use (including IBM

“bi-sync”). The USART accepts data characters from the CPU

in parallel format and then converts them into a continuous

serial data stream for transmission.

Simultaneously, it can receive serial data streams and

convert them into parallel data characters for the CPU. The

USART signals the CPU whenever it receives a character for

transmission or whenever it receives a character for the CPU.

The CPU can read the complete status of the USART at any

time, including data transmission errors and control signals

such as SYNDET and TxEMPTY.

FEATURES

Radiation Hard to 1MRad(Si)

Latch Up Free, High SEU Immunity

Silicon-on-Sapphire Technology

Synchronous 5 - 8 Bit Characters; Internal or External

Character Synchronisation; Automatic Sync Insertion

Asynchronous 5 - 8 Bit Characters; Clock Rate - 1, 16 or

64 Times Baud Rate; Break Character Generation, 1

⁄

2 Stop Bits

All Inputs and Outputs are TTL Compatible

Compatible with the MA31750 (MIL-STD-1750A & Draft

MIL-STD-1750B Option 2) Microprocessor

The MA8251 is based on the industry standard 8251A

USART, incorporating the following features:

1. MA8251 has double-buffered data paths with separate l/O

registers for control status, data in and data out, which

considerably simplifies control programming and minimizes

CPU overhead.

2. In synchronous operations, the Receiver detects and

handles “break” automatically, relieving the CPU of this task.

3. A refined Rx initialisation prevents the Receiver from

starting when in the “break” state, preventing unwanted

interrupts from the disconnected USART.

4. At the conclusion of a transmission, the TxD line will

always return to the marking state unless SBRK is

programmed.

5. Tx Enable logic enhancement prevents a Tx Disable

command from prematurely halting transmission of the

previously written data before completion. The logic also

prevents the transmitter from turning off in the middle of a

word.

6. When external Sync Detect is programmed, Internal Sync

Detect is disabled and an External Sync Detect status is

provided via a flip-flop, which clears itself upon a status read.

7. The possibility of a false sync detect is minimized in two

ways: by ensuring that if double character sync is

programmed, the characters will be continuously detected

and by clearing the Rx register to all 1’s whenever Enter-Hunt

command is issued in Sync mode.

8. When the MA8251 is not selected, the RDN and WRN

lines do not affect the internal operation of the device.

9. The MA8251 Status can be read at any time but the status

update will be inhibited during status read.

10. The MA8251 is free from extraneous glitches, providing

higher speed and better operating margins.

11. Synchronous Baud rate is from DC to 64K.

12. Asynchronous Baud rate is from DC to 19.2K.

Figure 1: MA8251 Block Diagram

MA8251

1. FUNCTIONAL DESCRIPTION

1.1 GENERAL

The MA8251 is a Universal Synchronous/Asynchronous

Receiver/Transmitter designed for use with the MA31750

microprocessor. Like other l/O devices in a microcomputer

system, its functional configuration is programmed by the

system’s software for maximum flexibility. The MA8251 can

support most serial data techniques in use, including IBM bi-

sync.

In a communication environment, an interface device must

convert parallel format system data into serial format for

transmission, and convert incoming serial data into parallel

system data for reception. The interface device must also

delete or insert bits or characters that are functionally unique to

the communication technique. In essence, the interface should

appear transparent to the CPU for the simple input or output of

byte-oriented system data.

1.6 WRITE STROBE (WRN)

A low on this signal line indicates that the CPU is writing

data or control information to the MA8251. The MA8251 clocks

data into its data input buffers on a rising edge of WRN.

1.7 CONTROL/DATA (CDN)

This input, in conjunction with the WRN and RDN inputs,

informs the MA8251 that the word on the Data Bus is either a

data character, control word or status information.

1 = CONTROL/STATUS; 0= DATA

CDN

RDN

WRN

CSN

ACTION

MA8251 to CPU

CPU to MA8251

Status to CPU

CPU to Control

Bus Tristate

1.2 DATA BUS BUFFER

This 3-state, bidirectional, 8-bit buffer is used to interface

the MA8251 to the system data bus. Data is transmitted or

received by the buffer upon execution of OUTput or INput

instructions from the CPU.

Control word, Command words and Status information are

also transferred through the Data Bus Buffer. The Command

Status, Data-in and Data-out registers are separate 8-bit

registers, communicating with the system bus through the

Data Bus Buffer.

This functional block accepts inputs from the system

control bus and generates control signals for overall device

operation. It contains the Control Word Register and

Command Word Register, which store the various control

formats for the device’s functional definition.

Figure 2: Read/Write Control

1.8 CHIP SELECT (CSN)

A low on this input selects the MA8251. No reading or

writing will occur unless the device is selected. When CSN is

high, the Data Bus is in the float state and the RDN and WRN

lines have no effect on the chip.

1.3 RESET

A high on this input forces the MA8251 into idle mode. The

MA8251 will remain at idle until its functional definition is

programmed with a new set of control words. Minimum RESET

pulse width is 6 tcy (clock must be running).

The device can also be put into the idle state by a

command reset operation .

1.9 MODEM CONTROL

The MA8251 has a set of control inputs and outputs which

can be used to simplify the interface to almost any modem.

The modem control signals are general purpose in nature and

can be used for functions other than modem control, if

necessary.

1.4 CLOCK (CLK)

The CLK input is used to generate internal device timing

and is normally connected to the clock generator (OSC) of the

system.

Please note: None of the external inputs or outputs are

referenced to CLK but the frequency of CLK must be greater

than 30 times the Receiver or Transmitter data bit rates.

1.10 DATA SET READY (DSR)

The

DSR

input signal is a general-purpose, 1-bit inverting

input port. Its condition can be tested by the CPU using a

Status Read operation. The

DSR

input is normally used to test

modem conditions such as Data Set Ready.

1.11 DATA TERMINAL READY (DTR)

The

DTR

output signal is a general purpose, 1-bit inverting

output port. It can be set low by programming the appropriate

bit in the Command instruction word. The

DTR

output signal is

normally used for modem control such as Data Terminal

Ready.

1.5 READ STROBE (RDN)

A low on this signal line indicates that the CPU is reading

data or status information from the MA8251. The MA8251

drives output data onto its data bus whilst this signal remains

low.

MA8251

1.12 REQUEST TO SEND (RTS)

The

RTS

output signal is a general purpose, 1-bit inverting

output port. It can be set low by programming the appropriate

bit in the Command instruction word. The

RTS

output signal is

normally used for modem control such as Request To Send.

1.18 TRANSMITTER CLOCK (TxC)

The Transmitter Clock controls the rate at which the

character is to be transmitted. In the Synchronous

transmission mode, the Baud Rate (1x) is equal to the

TxC

frequency. In Asynchronous transmission mode, the baud rate

is a fraction of the actual

TxC

frequency. A portion of the mode

instruction selects this factor; it can be 1,1/16 or 1/64 the

TxC.

For Example:

If Baud Rate equals 110 Baud

TxC

equals 110Hz in the 1x mode

TxC

equals 1.76kHz in the 16x mode

TxC

equals 7.04kHz in the 64x mode

The falling edge of

TxC

shifts the serial data out of the

MA8251.

1.13 CLEAR TO SEND (CTS)

A low on this input enables the MA8251 to transmit serial

data if the Tx Enable bit in the Command byte is set to a high.

If either a Tx Enable off or

CTS

off condition occurs while the

Tx is in operation, the Tx will transmit all the data in the

USART, written prior to Tx disable command, before shutting

down.

1.14 TRANSMITTER BUFFER

The Transmitter Buffer accepts parallel data from the Data

Bus Buffer, converts it to a serial bit stream, inserts the

appropriate characters or bits (based on the communication

technique) and outputs a composite serial stream of data on

the TxD output pin on the falling edge of

TxC.

The transmitter

will begin transmission upon being enabled if

CTS

= 0. The

TxD line will be held in the marking state immediately upon a

master Reset, or when Tx Enable or

CTS

= 1, or the

transmitter is empty.

1.19 RECEIVER BUFFER

The Receiver accepts serial data, converts the data to

parallel format, checks for bits or characters that are unique to

the communications techniques and sends an assembled

character to the CPU. Serial data is input to the RxD pin and is

clocked in on the rising edge of RxC.

1.15 TRANSMITTER CONTROL

The Transmitter Control manages all activities associated

with the transmission of serial data. It accepts and issues

signals both externally and internally to accomplish this

function.

1.16 TRANSMITTER READY (TxRDY)

This output signals the CPU that the transmitter is ready to

accept a data character. The TxRDY output pin can be used as

an interrupt to the system since it is masked by TxEnable; or,

for Polled operation, the CPU can check TxRDY using a Status

Read operation. TxRDY is automatically reset by the falling

edge of WRN when a data character is loaded from the CPU.

Note that when using the polled operation, the TxRDY

status bit is not masked by TxEnable, but will only indicate the

Empty/Full Status of the Tx Data input Register.

1.20 RECEIVER CONTROL

This functional block manages all receiver-related activities

which consist of the following features:

The RxD initialisation circuit prevents the MA8251 from

mistaking an unused input line for an active low data line in the

break condition. Before starting to receive serial characters on

the RxD line, a valid 1 must first be detected after a chip master

Reset. Once this has been determined, a search for a valid low

(start bit) is enabled. This feature is only active in the

asynchronous mode and is only done once for each master

Reset.

The False Start bit detection circuit prevents false starts as

the result of a transient noise spike by first detecting the falling

edge and then strobing the nominal center of the Start bit (RxD

= low).

Parity error detection sets the corresponding status bit.

The Framing Error status bit is set if the Stop bit is absent

at the end of the data byte (asynchronous mode).

1.17 TRANSMITTER EMPTY (TxE)

When the MA8251 has no characters to send, the

TxEMPTY output will go high. It resets upon receiving a

character from CPU if the transmitter is enabled. TxEMPTY

remains high when the transmitter is disabled. TxEMPTY can

be used to indicate the end of transmission mode, so that the

CPU can turn the line around in the half-duplex operational

mode.

In the Synchronous mode, a high on the TxEMPTY output

indicates that a character has not been loaded and the SYNC

character or characters are about to be or are being

automatically transmitted as fillers. TxEMPTY does not go low

when the SYNC characters are being shifted out.

1.21 RxRDY (RECEIVER READY)

This output indicates that the MA8251 contains a character

that is ready to be input to the CPU. RxRDY can be connected

to the interrupt structure of the CPU or, for polled operation,

the CPU can check the condition of RxRDY using a Status

Read operation. RxEnable, when off holds RxRDY in the

Reset Condition. For Asynchronous mode, to set RxRDY, the

Receiver must be enabled to sense a Start Bit and a complete

character must be assembled and transferred to the Data

Output Register. For Synchronous mode, to set RxRDY, the

Receiver must be enabled and a character must finish

assembly and be transferred to the Data Output Register.

MA8251

Failure to read the received character from the Rx Data

Output Register prior to the assembly of the next Rx Data

character will set overrun condition error and the previous

character will be written over and lost. If the Rx Data is being

read by the CPU when the internal transfer is occurring, the

overrun error will be set and the old character will be Iost.

1.24 BREAK (ASYNC MODE ONLY)

This output will go high whenever the receiver remains low

through two consecutive stop bit sequences including the start

bits, data bits, and parity bits. Break Detect may also be read

as a Status bit. It is reset only upon a master chip Reset or Rx

Data returning to a “one” state.

1.22

RxC

(RECEIVER CLOCK)

The Receiver Clock controls the rate at which the character

is to be received. In Synchronous Mode the Baud Rate (1x) is

equal to the actual frequency of

RxC.

In Asynchronous Mode,

the Baud Rate is a fraction of the actual

RxC

frequency. A

portion of the mode instruction selects this factor: 1,

⁄

the Receiver Clock.

For example:

Baud Rate equals 300 Baud, if

RxC

equals 300 Hz in the 1 x mode:

RxC

equals 4.8 kHz in the 16x mode

RxC

equals 19.2 kHz in the 64x mode.

Baud Rate equals 2400 Baud if

RxC

equals 2400 Hz in the 1x mode

RxC

equals 38.4 kHz in the 16x mode;

RxC

equals 153.6 kHz in the 64x mode.

Data is sampled into the MA8251 on the rising edge of

RxC.

Note: In most communications systems, the MA8251 will

be handling both the transmission and reception operations of

a single link. Consequently the Receive and Transmit Baud

Rates will be the same. Both

TxC

and

RxC

will require identical

frequencies for this operation and can be tied together and

connected to a single frequency source (Baud Rate

Generator) to simplify the interface.

C/D

ACTION

MODE INSTRUCTION

SYNC CHARACTER 1 (SYNC ONLY) *

SYNC CHARACTER 2 (SYNC ONLY) *

COMMAND INSTRUCTION

DATA

COMMAND INSTRUCTION

DATA

COMMAND INSTRUCTION

Note: The second sync character is skipped if mode instruction

has programmed the MA8251 to single character mode. Both

sync characters are skipped if mode instruction has

programmed the MA8251 to async mode

Figure 3: Typical data block

2. OPERATION DESCRIPTION

2.1 GENERAL

The complete functional definition of the MA8251 is

programmed by the system’s software. A set of control words

must be sent out by the CPU to initialize the MA8251 to

support the desired communications format. These control

words will program the: Baud Rate, Character Length, Number

of Stop Bits, Synchronous or Asynchronous Operation, Even/

Odd/Off Parity, etc. In the Synchronous Mode, options are also

provided to select either internal or external character

synchronization.

Once programmed, the MA8251 is ready to perform its

communication functions. The TxRDY output is raised high to

signal the CPU that the MA8251 is ready to receive a data

character from the CPU. This output (TxRDY) is reset

automatically when the CPU writes a character into the

MA8251. Alternatively, the MA8251 receives serial data from

the MODEM or l/O device. Upon receiving an entire character,

the RxRDY output is raised high to signal to the CPU that the

MA8251 has a complete character ready for the CPU to fetch.

RxRDY is reset automatically upon the CPU data read

operation.

The MA8251 cannot begin transmission until the TxEnable

(Transmitter Enable) bit is set in the Command instruction and

it has received a Clear To Send (CTS) input. The TxD output

will be held in the marking state upon Reset.

1.23 SYNC/BREAK DETECT (SYNDET/BRKDET)

This pin is used in Synchronous Mode for SYNDET and

may be used as either input or output, programmable through

the Control Word. It is reset to output mode, low upon RESET.

When used as an output (internal Sync mode), the SYNDET

pin will go high to indicate that the MA8251 has located the

SYNC character in the Receive mode. If the MA8251 is

programmed to use double Sync characters (bi-sync), the

SYNDET will go high in the middle of the last bit of the second

Sync character.

SYNDET is automatically reset upon a Status Read

operation.

When used as an input (external SYNC detect mode), a

positive going signal will cause the MA8251 to start

assembling data characters on the rising edge of the next

RxC.

Once in SYNC, the high input signal can be removed. When

External SYNC Detect is programmed, Internal SYNC Detect

is disabled.

MAS8251LL

MAS8251LL概述

MAS8251LL规格参数

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