1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Features
DDR3 SDRAM SODIMM
MT8JTF12864HY – 1GB
MT8JTF25664HY – 2GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as per
component data sheet
• 204-pin, small outline dual in-line memory module
(SODIMM)
• Fast data transfer rates: PC3-10600, PC3-8500,
or PC3-6400
• 1GB (128 Meg x 64), 2GB (256 Meg x 64)
• V
DD
= V
DD
Q = 1.5V ±0.075V
• V
DDSPD
= +3V to +3.6V
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single rank
• Eight internal device banks for concurrent operation
• Fixed burst length (BL) of 8 and burst chop (BC) of
4 via the mode register set
• Adjustable data-output drive strength
• Serial presence-detect (SPD) with EEPROM
• Gold edge contacts
• Pb-free
• Fly-by topology
• Terminated command, address, and control bus
Figure 1:
204-Pin SODIMM (MO-268 R/C B)
PCB height: 30mm (1.18in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Frequency/CAS latency
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.5ns @ CL = 10 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
–
2.5ns @ CL = 5 (DDR3-800)
–
2.5ns @ CL = 6 (DDR3-800)
1
Marking
None
I
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
Table 1:
Speed
Grade
-1G4
-1G3
-1G1
-1G0
-80C
-80B
Key Timing Parameters
Industry
Nomenclature
PC3-10600
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
Data Rate (MT/s)
CL = 10 CL = 9
–
1333
–
–
–
–
1333
1066
–
–
–
–
CL = 8
1066
800
–
1066
–
–
CL = 7
800
–
1066
800
–
–
CL = 6
–
–
800
–
–
800
CL = 5
–
–
–
–
800
–
t
RCD
t
RP
t
RC
(ns)
13.5
15
13.125
15
12.5
15
(ns)
13.5
15
13.125
15
12.5
15
(ns)
49.5
51
50.625
52.5
50
52.5
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. A 7/07 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
Addressing
1GB
8K
8K (A0–A13)
8 (BA0–BA2)
1KB
1Gb (128 Meg x 8)
1K (A0–A9)
1 (S0#)
2GB
8K
16K (A0–A14)
8 (BA0–BA2)
1KB
2Gb (256 Meg x 8)
1K (A0–A9)
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
Density
1GB
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
MT8JTF12864H(I)Y-1G4__
MT8JTF12864H(I)Y-1G3__
MT8JTF12864H(I)Y-1G1__
MT8JTF12864H(I)Y-1G0__
MT8JTF12864H(I)Y-80C__
MT8JTF12864H(I)Y-80B__
Configuration
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
128 Meg x 64
Table 4:
Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
Module
Bandwidth
10.6 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.5ns/1333 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
Clock Cycles
(CL-
t
RCD-
t
RP)
9-9-9
10-10-10
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
MT8JTF25664H(I)Y-1G4__
MT8JTF25664H(I)Y-1G3__
MT8JTF25664H(I)Y-1G1__
MT8JTF25664H(I)Y-1G0__
MT8JTF25664H(I)Y-80C__
MT8JTF25664H(I)Y-80B__
Notes:
Configuration
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
1. Data sheets for the base device parts can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT8JSF12864HY-1G1B1.
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. A 7/07 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
204-Pin SODIMM Front
204-Pin SODIMM Back
Symbol
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
DM6
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS7#
DQS7
V
SS
DQ62
DQ63
V
SS
NC
SDA
SCL
V
TT
Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
V
REF
DQ 53
55
V
SS
DQ0
57
DQ1
59
61
V
SS
DM0
63
V
SS
65
DQ2
67
DQ3
69
V
SS
71
DQ8
73
DQ9
75
V
SS
77
DQS1# 79
DQS1
81
V
SS
83
DQ10
85
DQ11
87
V
SS
89
DQ16
91
DQ17
93
V
SS
95
DQS2# 97
DQS2
99
V
SS
101
DQ18 103
DQ19
V
SS
DQ24
DQ25
V
SS
DM3
V
SS
DQ26
DQ27
V
SS
CKE0
V
DD
NC
BA2
V
DD
A12
A9
V
DD
A8
A5
V
DD
A3
A1
V
DD
CK0
CK0#
Notes:
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
V
DD
A10
BA0
V
DD
WE#
CAS#
V
DD
A13
NC
V
DD
NC
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DM5
V
SS
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DM7
V
SS
DQ58
DQ59
V
SS
SA0
V
DDSPD
SA1
V
TT
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
V
SS
54
V
SS
DQ4
56
DQ28
DQ5
58
DQ29
V
SS
60
V
SS
DQS0# 62
DQ3#
DQS0
64
DQ3
V
SS
66
V
SS
DQ6
68
DQ30
DQ7
70
DQ31
V
SS
72
V
SS
DQ12
74
NC
DQ13
76
V
DD
V
SS
78
NC
1
DM1
80 NC/A14
RESET# 82
V
DD
V
SS
84
A11
DQ14
86
A7
DQ15
88
V
DD
V
SS
90
A6
DQ20
92
A4
DQ21
94
V
DD
V
SS
96
A2
DM2
98
A0
V
SS
100
V
DD
DQ22 102
CK1
DQ23 104 CK1#
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
V
DD
BA1
RAS#
V
DD
S0#
ODT0
V
DD
NC
NC
V
DD
V
REF
CA
V
SS
DQ36
DQ37
V
SS
DM4
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS5#
DQS5
V
SS
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
1. Pin 80 is NC for 1GB and A14 for 2GB.
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. A 7/07 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A0–A13
(1GB)
A0–A14
(2GB)
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address and
auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0–BA2) or all banks (A10
HIGH). The address inputs also provide the op-code during a LOAD MODE command.
Referenced to V
REF
CA. When enabled in the mode register (MR), A12 is sampled during READ/
WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL
of 8 or no burst chop, LOW = BC of 4).
Bank address inputs:
BA0–BA2 define to which device bank an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA0–BA2 define which mode register, including MR,
EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
Clock enable:
CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking
circuitry on the DDR3 SDRAM.
Clock:
CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data
(DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Data input mask:
DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with that input data, during a write access. DM is sampled on both edges
of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and
DQS pins.
On-die termination:
ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being entered.
BA0–BA2
Input
CKE0
CK0, CK0#
Input
Input
DM0–DM7
Input
ODT0
Input
Input
Reset:
An active LOW CMOS input referenced to V
SS
and not referenced to V
REF
CA or V
REF
DQ.
(LVCMOS) The reset pin input receiver is a CMOS input and is defined as a rail-to-rail signal with a
DC HIGH
≥
0.8 × V
DD
Q and DC LOW
≤
0.2 × V
DD
Q (1.2V for HIGH and 0.3V for LOW). RESET#
assertion and desertion are asynchronous. System applications will most likely be
unterminated, heavily loaded, and have very slow slew rates. A slow slew rate receiver design
is recommended along with implementing on-chip noise filtering to prevent false triggering
(RESET# assertion minimum pulse width is 100ns).
SA0, SA1
Input
Presence-detect address inputs:
These pins are used to configure the presence-detect
device.
SCL
Input
Serial clock for presence-detect:
SCL is used to synchronize the communication to and from
the EEPROM.
S0#
Input
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
DQS0–DQS7,
I/O
Data strobe:
Output with read data, input with write data for source synchronous operation.
DQS0#–DQS7#
Edge-aligned with read data, center-aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE command.
DQ0–DQ63
I/O
Data input/output:
Bidirectional data bus.
SDA
I/O
Serial presence-detect data:
SDA is a bidirectional pin used to transfer addresses and data
into and out of the presence-detect portion of the module.
Supply
Power supply:
1.5V ±0.075V.
V
DD
Supply
Reference voltage:
DQ, DM. V
DD
/2.
V
REF
DQ
Supply
Reference voltage:
Command, address, and control. V
DD
/2.
V
REF
CA
Supply
Termination voltage:
Used for address, command, control, and clock nets. V
DD
/2.
V
TT
Supply
Ground.
V
SS
Supply
Serial EEPROM power supply:
+3V to +3.6V.
V
DDSPD
NC
–
No connect:
These pins should be left unconnected.
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. A 7/07 EN
RAS#, CAS#,
WE#
RESET#
Input
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR) 204-Pin DDR3 SDRAM SODIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
S0#
DQS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQS4#
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
U1
U3
DQS1#
DQS1
DM1
V
SS
DQS5#
DQS5
DM5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
V
SS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
U9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS2#
DQS2
DM2
V
SS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3#
DQS3
DM3
V
SS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQS6#
DQS6
DM6
V
SS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
U7
U2
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
V
SS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQS7#
DQS7
DM7
V
SS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
U4
U8
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
V
SS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
U6
BA0–BA2
A0–A13/A14
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
BA0–BA2: DDR3 SDRAM
A0–A13/A14: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
U5
SPD EEPROM
WP A0
A1
A2
CK0
CK0#
DDR3 SDRAM x 8
SDA
CK1
CK1#
V
SS
SA0 SA1
V
SS
V
DDSPD
Command, address, control, and clock line terminations:
CKE0, A0–A13/A14,
RAS#, CAS#, WE#,
S0#, ODT0, BA0–BA2
CK0
CK0#
SPD EEPROM
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
DDR3 SDRAM
V
DD
V
TT
V
REF
CA
DDR3
SDRAM
DDR3
SDRAM
V
TT
V
DD
V
REF
DQ
V
SS
Notes:
1. ZQ ball on each DDR3 component is connected to an external 240Ω resistor that is tied to
ground. Used for the calibration of the component’s on-die termination and output driver.
PDF: 09005aef82b36df5/Source: 09005aef82b36dc2
JSF8C128_256x6HY.fm - Rev. A 7/07 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
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