High Reliability Series Serial EEPROM Series
I C BUS
Serial EEPROMs
BR24G□□□ Series
□□□-3
□□□
BR24G01-3, BR24G02-3, BR24G04-3, BR24G08-3, BR24G16-3, BR24G32-3,
BR24G64-3, BR24G128-3, BR24G256-3
2
ROHM's series of serial EEPROMs represent the highest level of reliability on the market. A double cell structure provides a
failsafe method of data reliability, while a double reset function prevents data miswriting, pushing the boundaries of reliability
to the limit.
Contents
BR24G□□□
□□□-3
Series
□□□
BR24G01-3, BR24G02-3, BR24G04-3, BR24G08-3,
BR24G16-3, BR24G32-3, BR24G64-3, BR24G128-3,
BR24G256-3
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© 2011 ROHM Co., Ltd. All rights reserved.
1/19
2011.9 - Rev.A
BR24G□□□ Series
□□□-3
□□□
Technical Note
I
2
C BUS Serial EEPROMs
BR24G□□□ Series
□□□-3
□□□
BR24G01-3, BR24G02-3, BR24G04-3, BR24G08-3, BR24G16-3, BR24G32-3,
BR24G64-3, BR24G128-3, BR24G256-3
●Description
2
BR24G□□□-3 series is a serial EEPROM of I C BUS interface method
●Features
2
・
Completely conforming to the world standard I C BUS. All controls available by 2 ports of serial clock(SCL) and serial
data(SDA)
・
Other devices than EEPROM can be connected to the same port, saving microcontroller port
・
1.7V½5.5V single power source action most suitable for battery use
・
1.7V½5.5Ｖwide limit of action voltage, possible FAST MODE 400KHz action
・
Page write mode useful for initial value write at factory shipment
・
Auto erase and auto end function at data write
・
Low current consumption
・
Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
・
DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various package
・
Data rewrite up to 1,000,000 times
・
Data kept for 40 years
・
Noise filter built in SCL / SDA terminal
・
Shipment data all address FFh
●BR24G
series
Capacity
1Kbit
2Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
128Kbit
256Kbit
Bit format
128×8
256×8
512×8
1K×8
2K×8
4K×8
8K×8
16K×8
32K×8
Type
BR24G01-3
BR24G02-3
BR24G04-3
BR24G08-3
BR24G16-3
BR24G32-3
BR24G64-3
BR24G128-3
BR24G256-3
Power source
Voltage
SOP8
SOP-J8
SSOP-B8
TSSOP-B8
TSSOP-B8J
MSOP8
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
1.7½5.5V
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© 2011 ROHM Co., Ltd. All rights reserved.
2/19
2011.9 - Rev.A
BR24G□□□ Series
□□□-3
□□□
●Absolute
maximum ratings (Ta=25℃)
Parameter
Impressed voltage
symbol
V
CC
450 (SOP8)
Limits
-0.3½+6.5
*1
Technical Note
●Memory
cell characteristics (Ta=25℃, Vcc=1.7½5.5V)
Unit
V
Parameter
Number of data rewrite times
*1
Data hold years
*1
Limits
Min.
1,000,000
40
*1
Typ.
－
－
Max
－
－
Unit
Times
Years
450 (SOP-J8)
*2
300 (SSOP-B8)
Permissible
dissipation
Pd
*3
*4
330 (TSSOP-B8)
310 (MSOP8)
*6
310 (TSSOP-B8J)
*5
300 (VSON008X2030)
*7
800 (DIP-T8)
*8
mW
Not 100% TESTED
Storage temperature range
Action temperature range
Terminal voltage
Tstg
Topr
‐
－65½+150
－40½+85
－0.3½Vcc+1.0
*9
℃
℃
V
●Recommended
operating conditions
Parameter
Power source voltage
Input voltage
Symbol
Vcc
V
IN
Limits
1.7½5.5
0½Vcc
V
Unit
Junction Temperature
*10
Tjmax
150
℃
When using at Ta=25℃ or higher, 8.0mW(*8), 4.5mW(*1,*2),
3.0mW(*3,*7), 3.3mW(*4), 3.1mW(*5, *6) to be reduced per 1℃.
*9 The Max value of Terminal Voltage is not over 6.5V. When the pulse width is 50ns or less,
the Min value of Terminal Voltage is not under -1.0V. (BR24G16/32/64/128/256-3)
the Min value of Terminal Voltage is not under -0.8V. (BR24G01/02/04/08-3)
*10 Junction temperature at the storage condition.
●Electrical
characteristics
(Unless otherwise specified, Ta=－40½+85℃、VCC=1.7½5.5V)
Parameter
“H” input voltage 1
“L” input voltage 1
“L” output voltage 1
“L” output voltage 2
Input leak current
Output leak current
Symbol
V
IH1
V
IL1
V
OL1
V
OL2
I
LI
I
LO
●Action
timing characteristics
(Unless otherwise specified, Ta=－40½+85℃, VCC=1.7½5.5V)
Parameter
SCL frequency
Data clock “HIGH“ time
Symbol
Min.
fSCL
tHIGH
tLOW
tR
tF
tHD:STA
tSU:STA
tHD:DAT
tSU:DAT
tPD
tDH
tSU:STO
tBUF
tWR
tI
tHD:WP
tSU:WP
tHIGH:WP
－
0.6
1.2
－
－
0.6
0.6
0
100
0.1
0.1
0.6
1.2
－
－
1.0
0.1
1.0
Limit
Typ.
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
Max.
400
－
－
1.0
1.0
－
－
－
－
0.9
－
－
－
5
0.1
－
－
－
kHz
μs
μs
μs
μs
μs
μs
ns
ns
μs
μs
μs
μs
ms
μs
μs
μs
μs
Unit
Limits
Min.
0.7Vcc
－0.3
*1
－
－
－1
－1
－
Typ.
－
－
－
－
－
－
－
Max.
Vcc+1.0
0.3Vcc
0.4
0.2
1
1
2.0
Unit
V
V
V
V
µA
µA
Conditions
I
OL
=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
I
OL
=0.7mA, 1.7V≦Vcc＜2.5V (SDA)
V
IN
=0½Vcc
V
OUT
=0½Vcc (SDA)
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24G01/02/04/08/16/32/64-3
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24G128/256-3
Vcc=5.5V,f
SCL
=400kHz
Data clock “LOW“ time
SDA, SCL rise time
*1
SDA, SCL fall time
*1
Start condition hold time
Start condition setup time
Input data hold time
Input data setup time
Output data delay time
Output data hold time
Stop condition setup time
Bus release time before transfer start
Internal write cycle time
Noise removal valid period (SDA, SCL terminal)
WP hold time
WP setup time
WP valid time
I
CC1
Current consumption
at action
－
－
2.5
mA
I
CC2
－
－
0.5
mA
Random read, current read,
sequential read
BR24G01/02/04/08/16/32/64/128/256-3
Vcc=5.5V, SDA・SCL=Vcc
A0,A1,A2=GND,WP=GND
BR24G01/02/04/08/16/32/64/128/256-3
Standby current
I
SB
－
－
2.0
µA
○Radiation
resistance design is not made.
*1
When the pulse width is 50ns or less, it is -1.0V. (BR24G16/32/64/128/256-3)
When the pulse width is 50ns or less, it is -0.8V. (BR24G01/02/04/08-3)
*1 Not 100% TESTED.
Condition
Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing reference level: 0.3×Vcc/0.7×Vcc
Output data timing reference level: 0.3×Vcc/0.7×Vcc
Rise/Fall time :
≦20ns
●Sync
data input / output timing
tR
SCL
30%
70% 70%
30%
tF
tHIGH
70%
30%
70%
30%
70%
tLOW
tSU:DAT
70%
70%
70%
tHD:DAT
DATA(1)
D1
D0
ACK
DATA(n)
ACK
70%
70%
30%
SDA
(input)
SDA
(output)
tWR
30%
30%
tBUF
tPD
tDH
70%
30%
70%
30%
○
Input read at the rise edge of SCL
○
Data output in sync with the fall of SCL
tSU:WP
tHD:WP
STOP CONDITION
Fig.1-(a) Sync data input / output timing
70%
70%
70%
Fig.1-(d) WP timing at write execution
tSU:STA
70%
30%
tHD:STA
tSU:STO
DATA(1)
D1
30%
DATA(n)
ACK
tHIGH:WP
70%
70%
D0
ACK
70%
tWR
START CONDITION
STOP CONDITION
Fig.1-(b) Start-stop bit timing
D0
write data
(n-th address)
ACK
70%
70%
Fig.1-(e) WP timing at write cancel
tWR
STOP CONDITION
START CONDITION
Fig.1-(c) Write cycle timing
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© 2011 ROHM Co., Ltd. All rights reserved.
3/19
2011.9 - Rev.A
BR24G□□□ Series
□□□-3
□□□
●Block
diagram
*2
Technical Note
A0
1
*1
1Kbit
½
256 Kbit
EEPROM array
8bit
8
Vcc
A0
1
BR 24G01 -3
BR 24G02 -3
BR 24G04 -3
BR 24G08 -3
BR 24G16 -3
BR 24G32 -3
BR 24G64 -3
BR 24G128 -3
BR 24G256 -3
8
Vcc
*2
A1
2
Address
decoder
*1
7bit
13bit
8bit 14bit
9bit 15bit
10bit
11bit
12bit
Word
address register
Data
register
A1
7
WP
A2
2
7
WP
3
6
SCL
START
*2
STOP
A2
3
Control circuit
ACK
6
SCL
GND
4
5
SDA
GND
＊
4
High voltage
generating circuit
Power source
voltage detection
5
SDA
1
7bit: BR24G01-3
8bit: BR24G02-3
9bit: BR24G04-3
10bit: BR24G08-3
11bit: BR24G16-3
12bit: BR24G32-3
13bit: BR24G64-3
14bit: BR24G128-3
15bit: BR24G256-3
*2 A0= Don't use : BR24G04-3
A0, A1=Don't use : BR24G08-3
A0, A1, A2=Don't use : BR24G16-3
Fig.2
Block diagram
●Pin
assignment and description
Terminal
Name
A0
A1
A2
GND
SDA
SCL
WP
Vcc
Input/
Output
Input
Input
Input
－
Input/
output
Input
Input
－
Slave address setting
Slave address setting
Slave address setting
Don’t use＊
Don’t use＊
Don’t use＊
Slave address setting
Slave address setting
Slave address setting
BR24G01-3
BR24G02-3
BR24G04-3
BR24G08-3
BR24G16-3
BR24G32/64/128/256-3
Reference voltage of all input / output, 0V
Serial data input serial data output
Serial clock input
Write protect terminal
Connect the power source.
＊Pins
not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
●Characteristic
data (The following values are Typ. ones.)
6
6
1
L OUTPUT VOLTAGE : V
OL1
(V)
H INPUT VOLTAGE : V
IH1
(V)
L INPUT VOLTAGE : V
IL1
(V)
5
4
3
2
1
0
0
Ta=-40℃
Ta=25℃
Ta=85℃
5
4
3
2
1
Ta=-40℃
Ta=25℃
Ta=85℃
0.8
0.6
0.4
0.2
0
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SPEC
SPEC
0
0
1
2
3
4
5
6
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
0
1
SUPPLY VOLTAGE : Vcc(V)
2
3
4
5
L OUTPUT CURRENT : I
OL
(mA)
6
Fig.3 'H' input voltage V
IH1
(A0,A1,A2,SCL,SDA,WP)
1
L OUTPUT VOLTAGE : V
OL2
(V)
0.8
0.6
1.2
Fig.4 'L' input voltage V
IL1
(A0,A1,A2,SCL,SDA,WP)
1.2
OUTPUT LEAK CURRENT : I
LO
(uA)
Fig.5 'L' output voltage V
OL1
-I
OL
(Vcc=1.7V)
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
0.4
0.2
0
0
1
2
3
4
5
6
L OUTPUT CURRENT : I
OL
(mA)
INPUT LEAK CURRENT : I
LI
(uA)
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
SUPPLYVOLTAGE : Vcc(V)
SPEC
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Fig.6 'L' output voltage V
OL2
-I
OL
(Vcc=2.5V)
Fig.7 Input leak current I
LI
(A0,A1,A2,SCL,WP)
Fig.8 Output leak current I
LO
(SDA)
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© 2011 ROHM Co., Ltd. All rights reserved.
4/19
2011.9 - Rev.A
BR24G□□□ Series
□□□-3
□□□
●Characteristic
data (The following values are Typ. ones.)
2.5
Technical Note
3.5
0.6
SPEC
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
2
3
CURRENT CONSUMPTION
AT WRITING : Icc1(mA)
2.5
2
1.5
1
0.5
0
0
1
2
3
4
5
6
SPEC
SPEC
CURRENT CONSUMPTION
AT READING : Icc2(mA)
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
1.5
1
0.5
0
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.9 Current consumption at WRITE operation I
CC
1
(fscl=400kHz BR24G01/02/04/08/16/32/64-3)
2.5
SCL FREQUENCY : f½½½（½HZ）
STANDBY CURRENT : I
SB
(uA)
2
1.5
1
0.5
0
0
1
2
3
4
5
6
Fig.10 Current consumption at WRITE operation Icc1
(fscl=400kHz BR24G128/256-3)
10000
DATA CLK H TIME : t
HIGH
(us)
Fig.11 Current consumption at READ operation I
CC
2
(fscl=400kHz BR24G01/02/04/08/16/32/64/128/256-3)
1
0.8
0.6
0.4
0.2
0
SPEC
1000
SPEC
100
10
1
0.1
0
1
2
3
4
5
SUPPLY VOLTAGE : Vcc(V)
6
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.12 Standby operation ISB
(fscl=400kHz BR24G01/02/04/08/16/32/64/128/256-3)
START CONDITION HOLD TIME : t
HD : STA
(us)
Fig.13 SCL frequency fSCL
Fig.14 Data clock High Period t
HIGH
1.5
1
0.8
1.1
0.9
SPEC
ＤＡＴＡ CLK L TIME : t
LOW
(us)
1.2
0.9
0.6
0.3
0
0
1
2
3
4
5
6
SPEC
0.6
0.4
0.2
0
0
1
2
3
4
5
6
START CONDITION
SET UP TIME : t
SU:STA
(us)
0.7
0.5
0.3
0.1
-0.1
0
1
2
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
3
4
5
6
SUPPLY VOLTAGE : Vcc（V）
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.15 Data clock Low Period t
LOW
50
Fig.16 Start Condition Hold Time t
HD : STA
50
INPUT DATA SET UP TIME : t
SU: DAT
(ns)
Fig.17 Start Condition Setup Time t
SU : STA
300
200
INPUT DATA HOLD TIME : t
HD: STA
(ns)
INPUT DATA HOLD TIME : t
HD :DAT
(ns)
SPEC
0
-50
-100
-150
-200
0
1
2
3
4
5
6
SPEC
0
SPEC
100
0
-100
-200
0
1
2
3
4
5
6
-50
Ta=-40℃
Ta=25℃
Ta=85℃
-100
-150
-200
0
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.18 Input Data Hold Time t
HD : DAT
（HIGH）
300
200
100
0
-100
-200
0
1
2
3
4
5
6
2.0
Fig.19 Input Data Hold Time t
HD : DAT
(LOW）
Fig.20 Input Data Setup Time t
SU: DAT
(HIGH)
2.0
INPUT DATA SET UP TIME : t
SU : DAT
(ns)
OUTPUT DATA DELAY TIME : t
PD
(us)
1.5
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
OUTPUT DATA DELAY TIME : t
PD
(us)
1.5
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
1.0
1.0
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0.5
0.0
0
SPEC
1
2
3
4
5
6
0.0
0
SPEC
1
2
3
4
5
6
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
Fig.21 Input Data setup time t
SU : DAT
(LOW)
Fig.22 'L' Data output delay time t
PD
0
Fig.23 'H' Data output delay time t
PD
1
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5/19
2011.9 - Rev.A
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