PRELIMINARY DATASHEET
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
Description
The ICS270 field programmable VCXO clock synthesizer
generates up to eight high-quality, high-frequency clock
outputs including multiple reference clocks from a
low-frequency crystal input. It is designed to replace
crystals and crystal oscillators in most electronic systems.
Using IDT’s VersaClock
TM
software to configure PLLs and
outputs, the ICS270 contains a One-Time Programmable
(OTP) ROM for field programmability. Programming
features include VCXO, eight selectable configuration
registers and up to two sets of four low-skew outputs.
Using Phase-Locked Loop (PLL) techniques, the device
runs from a standard fundamental mode, inexpensive
crystal, or clock. It can replace VCXOs, multiple crystals
and oscillators, saving board space and cost.
The ICS270 is also available in factory programmed custom
versions for high-volume applications.
ICS270
Features
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Packaged as 20-pin TSSOP
Eight addressable registers
Replaces multiple crystals and oscillators
Output frequencies up to 200 MHz at 3.3 V
Input crystal frequency of 5 to 27 MHz
Up to eight reference outputs
Up to two sets of four low-skew outputs
Operating voltages of 3.3 V
Controllable output drive levels
Advanced, low-power CMOS process
Available in Pb (lead) free packaging
Block Diagram
VDD
3
S2:S0
3
OTP
ROM
with
PLL
Values
CLK1
PLL1
CLK2
Divide
Logic
and
Output
Enable
Control
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
PLL2
VIN
PLL3
X1
Crystal
X2
External capacitors
are required.
Voltage
Controlled
Crystal
Oscillator
GND
2
PDTS
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
1
ICS270
REV D 052008
ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
EPROM VCXO AND SYNTHESIZER
Pin Assignment
VIN
S0
S1
VDD
CLK1
CLK2
CLK3
CLK4
GND
X1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S2
VDD
PDTS
GND
CLK8
CLK7
CLK6
CLK5
VDD
X2
20 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
VIN
S0
S1
VDD
CLK1
CLK2
CLK3
CLK4
GND
X1
X2
VDD
CLK5
CLK6
CLK7
CLK8
GND
PDTS
VDD
S2
Pin
Type
Input
Input
Input
Power
Output
Output
Output
Output
Power
XI
XO
Power
Output
Output
Output
Output
Power
Input
Power
Input
Pin Description
Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO
frequency
Select pin 0. Internal pull-up resistor.
Select pin 1. Internal pull-up resistor.
Connect to +3.3 V.
Output clock 1. Weak internal pull-down when tri-state.
Output clock 2. Weak internal pull-down when tri-state.
Output clock 3. Weak internal pull-down when tri-state.
Output clock 4. Weak internal pull-down when tri-state.
Connect to ground.
Crystal input. Connect this pin to a crystal.
Crystal Output. Connect this pin to a crystal.
Connect to +3.3 V.
Output clock 5. Weak internal pull-down when tri-state.
Output clock 6. Weak internal pull-down when tri-state.
Output clock 7. Weak internal pull-down when tri-state.
Output clock 8. Weak internal pull-down when tri-state.
Connect to ground.
Power-down tri-state. Powers down entire chip and tri-states clock outputs
when low. Internal pull-up resisitor.
Connect to +3.3 V.
Select pin 2. Internal pull-up resisitor.
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
2
ICS270
REV D 052008
ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
EPROM VCXO AND SYNTHESIZER
External Components
The ICS270 requires a minimum number of external
components for proper operation.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω
.
The external crystal must be connected as close to the chip
as possible and should be on the same side of the PCB as
the ICS270. There should be no via’s between the crystal
pins and the X1 and X2 device pins. There should be no
signal traces underneath or close to the crystal. See
application note MAN05.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors on the
PCB is optional. The need for these capacitors is
determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture and
frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of your final
layout, a frequency counter capable of about 1 ppm
resolution and accuracy, two power supplies, and some
samples of the crystals which you plan to use in production,
along with measured initial accuracy for each crystal at the
specified crystal load capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the ICS270 to 3.3 V. Connect pin 1 of the
ICS270 to the second power supply. Adjust the voltage on
pin 1 to 0V. Measure and record the frequency of the CLK
output.
2. Adjust the voltage on pin 1 to 3.3 V. Measure and record
the frequency of the same output.
To calculate the centering error:
Decoupling Capacitors
As with any high-performance mixed-signal IC, the ICS270
must be isolated from system power supply noise to perform
optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. For
optimum device performance, the decoupling capacitor
should be mounted on the component side of the PCB.
Aboid the use of vias on the decoupling circuit.
Quartz Crystal
The ICS270 VCXO function consists of the external crystal
and the integrated VCXO oscillator circuit. To assure the
best system performance (frequency pull range) and
reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the following section shown must be
followed.
The frequency of oscillation of a quartz crystal is determined
by its “cut” and by the load capacitors connected to it. The
ICS270 incorporates on-chip variable load capacitors that
“pull” (change) the frequency of the crystal. The crystal
specified for use with the ICS270 is designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14 pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
°
C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
±20 ppm
±30 ppm
±20 ppm
14 pf
7 pF Max
250 Max
35Ω Max
6
(
f
3.0V
–
f
t arg et
)
+
(
f
0V
–
f
t arg et
)
-
Error = 10 x ----------------------------------------------------------------------
–
error
xtal
f
t arg et
Where:
f
target
= nominal crystal frequency
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
3
ICS270
REV D 052008
ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
EPROM VCXO AND SYNTHESIZER
error
xtal
=actual initial accuracy (in ppm) of the crystal being
measured
If the centering error is less than ±25 ppm, no adjustment is
needed. If the centering error is more than 25ppm negative,
the PC board has excessive stray capacitance and a new
PCB layout should be considered to reduce stray
capacitance. (Alternately, the crystal may be re-specified to
a higher load capacitance. Contact IDT for details.) If the
centering error is more than 25 ppm positive, add identical
fixed centering capacitors from each crystal pin to ground.
The value for each of these caps (in pF) is given by: External
Capacitor = 2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied by your
crystal vendor. If you do not know the value, assume it is 30
ppm/pF. After any changes, repeat the measurement to
verify that the remaining error is acceptably low (typically
less than ±25 ppm).
IDT VersaClock Software
IDT applies years of PLL optimization experience into a user
friendly software that accepts the user’s target reference
clock and output frequencies and generates the lowest jitter,
lowest power configuration, with only a press of a button.
The user does not need to have prior PLL experience or
determine the optimal VCO frequency to support multiple
output frequencies.
VersaClock software quickly evaluates accessible VCO
frequencies with available output divide values and provides
an easy to understand, bar code rating for the target output
frequencies. The user may evaluate output accuracy,
performance trade-off scenarios in seconds.
ICS270 Configuration Capabilities
The architecture of the ICS270 allows the user to easily
configure the device to a wide range of output frequencies,
for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be set
within the range of M = 1 to 1024 and N = 1 to 32,895.
The ICS270 also provides separate output divide values,
from 2 through 63, to allow the two output clock banks to
support widely differing frequency values from the same
PLL.
Each output frequency can be represented as:
OutputFreq
=
REFFreq
⋅
M
----
-
N
Output Drive Control
The ICS270 has two output drive settings. Low drive should
be selected when outputs are less than 100 MHz. High drive
should be selected when outputs are greater than 100 MHz.
(Consult the AC Electrical Characteristics for output rise and
fall times for each drive option.)
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
4
ICS270
REV D 052008
ICS270
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
EPROM VCXO AND SYNTHESIZER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS270. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Parameter
Supply Voltage, VDD
Inputs
Clock Outputs
Storage Temperature
Soldering Temperature
Junction Temperature
Condition
Referenced to GND
Referenced to GND
Referenced to GND
Max 10 seconds
Min.
-0.5
-0.5
-65
Typ.
Max.
7
VDD+0.5
VDD+0.5
150
260
125
Units
V
V
V
°
C
°
C
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (ICS270PG/PGLF)
Ambient Operating Temperature (ICS270PGI/PGILF)
Power Supply Voltage (measured in respect to GND)
Power Supply Ramp Time
Reference crystal parameters
Min.
0
-40
+3.135
Typ.
Max.
+70
+85
Units
°
C
°
C
V
ms
+3.3
+3.465
4
Refer to page 3
IDT™ / ICS™
TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK
5
ICS270
REV D 052008
FPGA/CPLD
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